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m ? core ? MMC2001 reference manual motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. the m ?core name and logotype and the once name are trademarks of motorola, inc. ? motorola, inc. 1998

MMC2001 motorola reference manual iii conventions this document uses the following notational conventions: mnemonics instruction mnemonics are shown in lowercase bold 0x0f hexadecimal numbers 0b0011 binary numbers nomenclature logic level one is the voltage that corresponds to a boolean true (1) state. logic level zero is the voltage that corresponds to a boolean false (0) state. to set a bit or bits means to establish logic level one on the bit or bits. to clear a bit or bits means to establish logic level zero on the bit or bits. lsb means least significant bit or bits. msb means most significant bit or bits. refer- ences to low and high bytes are spelled out. a signal is asserted when it is in its active or true state, regardless of whether that state is represented by a high or low voltage. a signal is negated when it is in its inac- tive or false state.
motorola MMC2001 iv reference manual
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MMC2001 motorola reference manual xv list of illustrations paragraph title page 1-1 MMC2001 block diagram ................................................................................ 1-2 2-1 programming model......................................................................................... 2-4 2-2 data organization in memory .......................................................................... 2-5 2-3 data organization in registers ........................................................................ 2-5 2-4 signal relationships to clocks......................................................................... 2-9 2-5 m?core bus signals .................................................................................... 2-10 2-6 external multiplexer connections................................................................... 2-13 4-1 functional signal groups................................................................................. 4-1 7-1 eim block diagram .......................................................................................... 7-1 7-2 eim interface to memory and peripherals........................................................ 7-4 7-3 cs0 control register ....................................................................................... 7-7 7-4 cs1 , cs2 , cs3 control registers ................................................................... 7-8 7-5 eim configuration register ............................................................................ 7-11 7-6 read memory access (csa = 0, wsc = 1)................................................... 7-14 7-7 write memory access (csa = 0, wsc = 1, wws = 0) ................................. 7-15 7-8 word read access from halfword width memory......................................... 7-16 7-9 word write access to halfword width memory ............................................. 7-17 7-10 write after read memory access (csa = 0, wsc = 2, edc = 0) ................. 7-18 7-11 write after read memory access (csa = 0, wsc = 1, edc = 1) ................. 7-19 7-12 peripheral read access (csa = 1, wsc = 5) ............................................... 7-20 7-13 peripheral write access (csa = 1, wsc = 5) ............................................... 7-21 7-14 read and write fast memory access (csa = 0, wsc = 0, wws = 0)......... 7-22 8-1 MMC2001 clock module.................................................................................. 8-3 9-1 reset functional block diagram...................................................................... 9-2 9-2 reset source register ..................................................................................... 9-3 9-3 tod block diagram ......................................................................................... 9-4 9-4 tod control/status register ........................................................................... 9-5 9-5 tod seconds register .................................................................................... 9-6 9-6 tod fraction register ..................................................................................... 9-7 9-7 tod seconds alarm register.......................................................................... 9-7 9-8 tod fraction alarm register........................................................................... 9-8 9-9 watchdog timer block diagram ...................................................................... 9-8 9-10 watchdog control register ............................................................................ 9-10 9-11 watchdog service register............................................................................ 9-11 9-12 pit block diagram ......................................................................................... 9-12 9-13 starting a count from an off state................................................................. 9-12 9-14 counter reloading from the modulus latch................................................... 9-13 9-15 counter in free-running mode...................................................................... 9-13 9-16 pit control and status register .................................................................... 9-14 9-17 pit data register........................................................................................... 9-15 9-18 pit alternate data register ........................................................................... 9-16 10-1 interrupt source register ............................................................................... 10-2 10-2 normal interrupt enable register................................................................... 10-3
motorola MMC2001 xvi reference manual list of illustrations paragraph title page 10-3 fast interrupt enable register ....................................................................... 10-3 10-4 normal interrupt pending register................................................................. 10-4 10-5 fast interrupt pending register ..................................................................... 10-5 11-1 uart channel block diagram....................................................................... 11-2 11-2 uart receive register ................................................................................. 11-7 11-3 uart transmitter register............................................................................ 11-9 11-4 uart control register 1 ............................................................................... 11-9 11-5 uart control register 2 ............................................................................. 11-12 11-6 uart brg register .................................................................................... 11-13 11-7 uart status register.................................................................................. 11-14 11-8 uart test register ..................................................................................... 11-15 11-9 uart port control register......................................................................... 11-16 11-10 uart data direction register ..................................................................... 11-16 11-11 uart port data register............................................................................. 11-17 11-12 start bit ideal case.................................................................................. 11-19 11-13 start bit noise case one ........................................................................ 11-20 11-14 start bit noise case two ........................................................................ 11-21 11-15 start bit noise case three...................................................................... 11-22 11-16 start bit noise case four........................................................................ 11-23 12-1 ispi channel block diagram.......................................................................... 12-1 12-2 timing diagram of ispi 8-bit operation......................................................... 12-2 12-3 ispi data register ......................................................................................... 12-5 12-4 ispi control register ..................................................................................... 12-5 12-5 ispi interval control register......................................................................... 12-8 12-6 ispi status register....................................................................................... 12-8 13-1 external interrupt/gpio block diagram ......................................................... 13-1 13-2 edge port pin assignment register............................................................... 13-2 13-3 edge port data direction register ................................................................. 13-3 13-4 edge port data register ................................................................................ 13-3 13-5 edge port flag register................................................................................. 13-4 14-1 kpp block diagram........................................................................................ 14-1 14-2 keypad control register ................................................................................ 14-3 14-3 keypad status register ................................................................................. 14-4 14-4 keypad data direction register..................................................................... 14-5 14-5 keypad data register .................................................................................... 14-5 14-6 keypad synchronizer functional diagram..................................................... 14-8 14-7 decoding wrong three key presses............................................................. 14-9 15-1 pwm block diagram ...................................................................................... 15-1 15-2 pwm generating audio ................................................................................. 15-1 15-3 pwm prescaler .............................................................................................. 15-2 15-4 pwm control registers.................................................................................. 15-4 15-5 pwm period registers................................................................................... 15-6 15-6 pwm width registers .................................................................................... 15-7
MMC2001 motorola reference manual xvii list of illustrations paragraph title page 15-7 pwm count registers.................................................................................... 15-7 16-1 once block diagram ..................................................................................... 16-1 16-2 once controller............................................................................................. 16-2 16-3 once controller and serial interface............................................................. 16-4 16-4 once command register ............................................................................. 16-7 16-5 once control register .................................................................................. 16-8 16-6 once status register.................................................................................. 16-11 16-7 once memory breakpoint logic.................................................................. 16-13 16-8 once trace logic block diagram ............................................................... 16-15 16-9 cpu scan chain register (cpuscr) ......................................................... 16-17 16-10 control state register.................................................................................. 16-18 16-11 once pc fifo ............................................................................................ 16-20 16-12 recommended connector interface to jtag/once port............................ 16-22 a-1 clkin timing (for square wave input) ...........................................................a-2 a-2 reset timing ....................................................................................................a-3 a-3 mod timing .....................................................................................................a-3 a-4 external interrupt timing..................................................................................a-4 a-5 eim read/write timing ....................................................................................a-5 a-6 spi slave timing (pha = 0).............................................................................a-7 a-7 spi slave timing (pha = 1).............................................................................a-7 a-8 spi manual/interval mode timing (pha = 0) ...................................................a-8 a-9 spi manual/interval mode timing (pha = 1) ...................................................a-8 a-10 test clock input timing ...................................................................................a-9 a-11 trst timing ....................................................................................................a-9 a-12 test access port timing ................................................................................a-10 b-1 144-lead plastic thin quad flat pack pin assignment...................................b-1 c-1 interrupt source register .................................................................................c-2 c-2 normal interrupt enable register.....................................................................c-3 c-3 fast interrupt enable register .........................................................................c-3 c-4 normal interrupt pending register...................................................................c-4 c-5 fast interrupt pending register .......................................................................c-4 c-6 reset source register .....................................................................................c-6 c-7 tod control/status register ...........................................................................c-7 c-8 tod seconds register ....................................................................................c-8 c-9 tod fraction register .....................................................................................c-8 c-10 tod seconds alarm register..........................................................................c-9 c-11 tod fraction alarm register...........................................................................c-9 c-12 watchdog control register ............................................................................c-10 c-13 watchdog service register............................................................................c-11 c-14 pit control and status register ....................................................................c-11 c-15 pit data register...........................................................................................c-13 c-16 pit alternate data register ...........................................................................c-13 c-17 keypad control register ................................................................................c-14
motorola MMC2001 xviii reference manual list of illustrations paragraph title page c-18 keypad status register .................................................................................c-14 c-19 keypad data direction register.....................................................................c-15 c-20 keypad data register ....................................................................................c-16 c-21 cs0 control register .....................................................................................c-17 c-22 cs1 , cs2 , cs3 control registers .................................................................c-17 c-23 eim configuration register ............................................................................c-21 c-24 pwm control registers..................................................................................c-23 c-25 pwm period registers...................................................................................c-26 c-26 pwm width registers ....................................................................................c-26 c-27 pwm count registers....................................................................................c-27 c-28 edge port pin assignment register...............................................................c-28 c-29 edge port data direction register .................................................................c-28 c-30 edge port data register ................................................................................c-29 c-31 edge port flag register.................................................................................c-29 c-32 ispi data register .........................................................................................c-30 c-33 ispi control register .....................................................................................c-31 c-34 ispi interval control register.........................................................................c-33 c-35 ispi status register.......................................................................................c-34 c-36 uart receive register .................................................................................c-36 c-37 uart transmit register ................................................................................c-37 c-38 uart control register 1 ...............................................................................c-38 c-39 uart control register 2 ...............................................................................c-40 c-40 uart brg register ......................................................................................c-42 c-41 uart status register....................................................................................c-42 c-42 uart test register .......................................................................................c-44 c-43 uart port control register...........................................................................c-44 c-44 uart data direction register .......................................................................c-45 c-45 uart port data register...............................................................................c-45 c-46 once command register .............................................................................c-46 c-47 once control register ..................................................................................c-47 c-48 once status register....................................................................................c-50 c-49 control state register....................................................................................c-52
MMC2001 motorola reference manual xix list of tables paragraph title page 2-1 m?core instruction set ................................................................................. 2-6 2-2 m?core bus signals .................................................................................. 2-11 2-3 interface requirements for read and write cycles....................................... 2-12 2-4 termination result summary......................................................................... 2-14 3-1 MMC2001 module address map...................................................................... 3-1 3-2 MMC2001 address map .................................................................................. 3-2 4-1 pin requirements in 144-pin package .......................................................... 4-2 5-1 rom module address map.............................................................................. 5-1 6-1 static ram module address map .................................................................... 6-1 7-1 chip select address range ............................................................................. 7-3 7-2 interface requirements for read and write cycles ....................................... 7-5 7-3 eim memory map ............................................................................................ 7-7 7-4 wait state control field settings .................................................................... 7-9 7-5 data port size field settings ......................................................................... 7-10 7-6 show cycle enable field settings ................................................................. 7-13 8-1 cpu core and peripherals clock source ........................................................ 8-1 8-2 cpu core and peripherals in low-power modes ............................................ 8-7 9-1 timer/reset module address map .................................................................. 9-1 10-1 interrupt controller address map .................................................................. 10-2 10-2 interrupt source assignment ........................................................................ 10-6 11-1 uart module address map .......................................................................... 11-6 11-2 txfl field settings ........................................................................................ 11-9 11-3 rxfl field settings...................................................................................... 11-10 11-4 uart pins gpio assignment...................................................................... 11-16 11-5 uart low-power mode operation.............................................................. 11-23 12-1 ispi module address map ............................................................................. 12-4 12-2 baud rate field settings............................................................................ 12-7 12-3 clock count field settings ...................................................................... 12-7 12-4 ispi low-power mode operation................................................................. 12-11 13-1 gpio edge port address map ...................................................................... 13-2 13-2 eppax field settings ..................................................................................... 13-3 14-1 keypad port column modes .......................................................................... 14-2 14-2 keypad port address map ............................................................................ 14-2 15-1 pwm address map ........................................................................................ 15-3 15-2 clk sel field settings.................................................................................. 15-6 15-3 pwm range at 16 mhz ................................................................................. 15-8 15-4 pwm low-power mode operation................................................................. 15-8 16-1 once register addressing ........................................................................... 16-8 16-2 sequential control field settings................................................................... 16-9 16-3 memory breakpoint control field settings................................................... 16-10 16-4 processor mode field settings .................................................................... 16-12 a-1 maximum ratings ............................................................................................a-1 a-2 dc electrical specifications ...........................................................................a-1
motorola MMC2001 xx reference manual list of tables paragraph title page a-3 clock input specifications ................................................................................a-2 a-4 reset, mod timing specifications ................................................................a-2 a-5 external interrupt timing specifications...........................................................a-3 a-6 eim timing specifications................................................................................a-4 a-7 ispi timing specifications ...............................................................................a-6 a-8 once timing specifications ............................................................................a-9 c-1 MMC2001 address map ..................................................................................c-1 c-2 interrupt controller address map ....................................................................c-2 c-3 timer/reset module address map .................................................................c-5 c-4 keypad port address map ............................................................................c-13 c-5 eim address map ..........................................................................................c-16 c-6 wait state control field settings ..................................................................c-18 c-7 data port size field settings .........................................................................c-19 c-8 chip-select address range...........................................................................c-20 c-9 show cycle enable field settings .................................................................c-22 c-10 pwm address map ......................................................................................c-22 c-11 clock select field values ..............................................................................c-25 c-12 gpio edge port address map ......................................................................c-27 c-13 eppax field settings .....................................................................................c-28 c-14 interval mode serial peripheral interface address map.................................c-30 c-15 baud rate values.......................................................................................c-32 c-16 clock count values .................................................................................c-33 c-17 uart module address map ..........................................................................c-35 c-18 txfl field settings ........................................................................................c-38 c-19 rxfl field settings........................................................................................c-39 c-20 once register addressing ............................................................................c-47 c-21 sequential control field definition.................................................................c-48 c-22 memory breakpoint control field definition...................................................c-49 c-23 processor mode field definition ....................................................................c-51
MMC2001 introduction motorola reference manual 1-1 section 1 introduction the MMC2001 integrated processor incorporates the following functional units: ? m?core? integer processor 32-bit risc architecture low power, high performance ? on-chip, 256-kbyte rom ? on-chip, 32-kbyte sram with battery backup supply support ? interrupt controller support for up to 32 interrupt sources ? external interface module (eim) transfers information between the MMC2001 and external memory or periph- erals 20 address lines 16 data lines chip select and wait state generation bus watchdog timer ? timer/reset module crystal oscillator: generates the master clock signal for the time-of-day timer from a 32.768-khz external crystal time-of-day timer: provides time-of-day information as well as an alarm clock function watchdog timer: resets the chip to recover from system failure reset unit: provides low voltage detection input and backup power switching for sram and the time-of-day timer periodic interrupt timer ? universal asynchronous receiver/transmitter module (uart) two independent uart channels asynchronous operation baud rate generation infrared (ir) interface support ? 16-bit general-purpose i/o port with support for keyboard scan/encode ? 8-bit general-purpose i/o port with support for edge/level sensitive external inter- rupts ? pulse-width modulation module (pwm) six independent pwm channels programmable period programmable duty cycle periodic interrupt capability pins can be configured as general-purpose i/o ? interval mode serial peripheral interface (ispi) efficient communication with slower serial peripherals
motorola introduction MMC2001 1-2 reference manual designed for master/slave spi operation interval-mode spi operation ? once? debug module as a low-voltage part, the MMC2001 operates at voltages between 2.0 and 3.3 volts. it is particularly suited for use in battery-powered applications. the internal logic and external i/o buffers are provided with independent power sup- ply connections to allow 3.3-v i/o levels while operating internal logic at 2.0 v for lower power consumption. figure 1-1 MMC2001 block diagram m?core 32-bit 32-kbyte sram 20-bit address bus 16-bit data bus control clk watchdog memory controller tod reset ispi osc 256-kbyte rom periodic interval once pwm x 6 uart x 2 timer gen gpio/ keypad interrupt risc cpu peripheral interface gasket
MMC2001 integer cpu motorola reference manual 2-1 section 2 integer cpu this section gives a short description of the m?core cpu features and some basic bus interface information. 2.1 m?core overview the 32-bit m?core microrisc engine represents a new family of motorola micro- processor core products. the processor architecture has been designed for high-per- formance and cost-sensitive embedded control applications, with particular emphasis on reduced system power consumption. this makes the m?core suitable for bat- tery-operated, portable products, as well as for highly integrated parts designed for a high temperature environment. total system power consumption is dictated by various components in addition to the processor core. in particular, memory power consumption (both on-chip and external) is expected to dominate overall power consumption of the core-plus-memory sub- system. with this factor in mind, the instruction set architecture (isa) for m?core makes the trade-off of absolute performance capability versus total energy consump- tion in favor of reducing the overall energy consumption, while maintaining an accept- ably high level of performance at a given clock frequency. m?core is a streamlined execution engine that provides many of the same perfor- mance enhancements as mainstream reduced instruction set computer (risc) designs. fixed length instruction encoding and a strict load/store architecture mini- mize control complexity and overhead. the goal of minimizing the overhead of mem- ory system energy consumption is achieved by adopting a (relatively) short 16-bit instruction encoding. this choice significantly lowers the memory bandwidth needed to sustain a high rate of instruction execution. code density statistics for a number of applications show relative code density com- petitive in comparison to complex instruction set computer (cisc) designs, and implementation statistics show a large reduction in complexity and overhead relative to a cisc approach. in addition to substantial cost and performance benefits, m?core also offers advan- tages in power consumption and power management. m?core minimizes power dis- sipation by using a fully static design, dynamic power management, and low-voltage operation. the m?core automatically powers-down internal functional blocks that are not needed on a clock-by-clock basis. power conservation modes are also pro- vided for absolute power conservation on a coarser granularity.
motorola integer cpu MMC2001 2-2 reference manual 2.2 features the main features of the m?core are as follows: ? 32-bit load/store risc architecture ? fixed 16-bit instruction length ? 16-entry, 32-bit general-purpose register file ? efficient 4-stage execution pipeline, hidden from application software ? single-cycle instruction execution for many instructions ? two cycles for taken branches and memory access instructions ? support for byte, halfword, and word memory accesses ? fast interrupt support with 16-entry dedicated alternate register file ? vectored and autovectored interrupt support 2.3 microarchitecture summary the m?core instruction execution pipeline consists of the following stages: ? instruction fetch ? instruction decode/register file read ? execute ? register writeback these stages operate in an overlapped fashion, allowing single-clock instruction exe- cution for most instructions. sixteen general-purpose registers are provided for source operands and instruction results. register r15 is used as the link register to hold the return address for sub- routine calls, and register r0 is associated with the current stack pointer value by convention. the execution unit consists of a 32-bit arithmetic/logic unit (alu), a 32-bit barrel shifter, a find-first-one unit (ffo), result feed-forward hardware, and miscellaneous support hardware for multiplication and multiple register loads and stores. arithmetic and logical operations are executed in a single cycle with the exception of the multi- ply, signed divide, and unsigned divide instructions. the multiply instruction is imple- mented with a 2-bit per clock, overlapped-scan, modified booth algorithm with early- out capability to reduce execution time for operations with small multiplier values. the signed divide and unsigned divide instructions also have data-dependent timing. a find-first-one unit operates in a single clock cycle. the program counter unit has a pc incrementer and a dedicated branch address adder to minimize delays during change of flow operations. branch target addresses are calculated in parallel with branch instruction decode, with a single pipeline bubble for taken branches and jumps. this results in an execution time of two clocks. condi- tional branches that are not taken execute in a single clock. memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero extension of byte and halfword load data. these instructions can execute in two clock cycles. load and store multiple register instructions allow low overhead context save and restore operations. these instructions can execute in (n+1) clock cycles, where n is the numbers of registers to transfer.
MMC2001 integer cpu motorola reference manual 2-3 a single condition code/carry (c) bit is provided for condition testing and for use in implementing arithmetic and logical operations greater than 32 bits. typically, the c- bit is set only by explicit test/comparison operations, not as a side-effect of normal instruction operation. exceptions to this rule occur for specialized operations for which it is desirable to combine condition setting with actual computation. a 16-entry alternate register file is provided to support low overhead interrupt excep- tion processing. the cpu supports both vectored and autovectored interrupts. 2.4 programming model the m?core programming model is defined separately for two privilege modes: supervisor and user. certain operations are not available in user mode. user programs can only access registers specific to the user mode; system software executing in the supervisor mode can access all registers, using the control registers to perform supervisory functions. user programs are thus restricted from accessing privileged information. the operating system performs management and service tasks for the user programs by coordinating their activities. most instructions execute in either mode, but some instructions that have important system effects are privileged and can only execute in the supervisor mode. for instance, user programs cannot execute the stop , doze , or wait instructions. to pre- vent a user program from entering the supervisor mode except in a controlled man- ner, instructions that can alter the s bit in the program status register (psr) are privileged. the trap #n instructions provide controlled access to operating system services for user programs. access to special control registers is also precluded in user mode. when the s bit in the psr is set, the processor executes instructions in the supervi- sor mode. bus cycles associated with an instruction indicate either supervisor or user access depending on the mode. the processor uses the user programming model during normal user mode process- ing. during exception processing, the processor changes from user to supervisor mode. exception processing saves the current value of the psr in the epsr or fpsr shadow control register and then sets the s bit in the psr, forcing the proces- sor into the supervisor mode. to return to the previous operating mode, a system rou- tine may execute the rte (return from exception) or rfi (return from fast interrupt) instruction as appropriate, causing the instruction pipeline to be flushed and refilled from the appropriate address space. the registers depicted in the programming model (see figure 2-1 ) provide operand storage and control. the registers are partitioned into two levels of privilege: user and supervisor. the user programming model consists of 16 general-purpose 32-bit regis- ters, the 32-bit program counter (pc) and the condition/carry (c) bit. the c bit is implemented as bit 0 of the psr. this is the only portion of the psr accessible by the user. the supervisor programming model consists of 16 additional 32-bit general-pur- pose registers (the alternate file), as well as a set of status/control registers and scratch registers. by convention, register r15 serves as the link register for subrou- tine calls, and register r0 is typically used as the current stack pointer.
motorola integer cpu MMC2001 2-4 reference manual the alternate file is selected for use via a control bit in the psr. the status, control, and scratch registers are accessed via the move from control register ( mfcr ) and move to control register ( mtcr ) instructions. when the alternate file is selected via the af bit in the psr, general-purpose operands are accessed from it. when the af bit is cleared, operands are accessed from the normal file. this alternate file is provided to allow very low overhead context switching capability for real-time event handling. figure 2-1 programming model the supervisor programming model includes the psr, which contains operation con- trol and status information. in addition, a set of exception shadow registers is pro- vided to save the state of the psr and the program counter at the time an exception occurs. a separate set of shadow registers is provided for fast interrupt support to minimize context saving overhead. five scratch registers are provided for supervisor software use in handling exception events. a single register is provided to alter the base address of the exception vector table. two registers are provided for global control and status. r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r12 r13 r14 r15 r11 r10 c r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r12 r13 r14 r15 r11 r10 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r12 r13 r14 r15 r11 r10 user programmers model alternate file supervisor programmers model pc pc c * bit 0 of psr psr vbr epsr fpsr epc fpc ss0 ss1 ss2 cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 ss4 cr10 gcr cr11 ss3 gsr cr12
MMC2001 integer cpu motorola reference manual 2-5 2.5 data format summary the operand data formats supported by the integer unit are standard twos-comple- ment data formats. the operand size for each instruction is either explicitly encoded in the instruction (load/store instructions) or implicitly defined by the instruction opera- tion (index operations, byte extraction). typically, instructions operate on all 32 bits of the source operand(s) and generate a 32-bit result. memory is viewed from a big-endian byte ordering perspective. the most significant byte (byte 0) of word 0 is located at address 0. bits are numbered within a word start- ing with bit 31 as the most significant bit. figure 2-2 data organization in memory figure 2-3 data organization in registers byte 0 byte 1 byte 2 byte 3 word at 0 31 0 byte 4 byte 5 byte 6 byte 7 word at 4 byte 8 byte 9 byte a byte b word at 8 byte c byte d byte e byte f word at c byte signed byte s s s s s s s s s s s s s s s s s s s s s s s s s 0 8 7 31 byte unsigned byte 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 31 halfword signed s s s s s s s s s s s s s s s s s 0 16 15 31 halfword halfword unsigned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 15 31 halfword 0 31 word byte 3 byte 2 byte 1 byte 0
motorola integer cpu MMC2001 2-6 reference manual 2.6 operand addressing capabilities m?core accesses all memory operands through load and store instructions, trans- ferring data between the general-purpose registers and memory. register-plus-four- bit scaled displacement addressing mode is used for the load and store instructions to address byte, halfword, or word (32-bit) data. load and store multiple instructions allow a subset of the 16 gprs to be transferred to or from a base address pointed to by register r0 (the default stack pointer by con- vention). load and store register quadrant instructions use register indirect addressing to transfer a register quadrant to or from memory. 2.7 instruction set overview the instruction set is tailored to support high-level languages and is optimized for those instructions most commonly executed. a standard set of arithmetic and logical instructions is provided, as well as instruction support for bit operations, byte extrac- tion, data movement, control flow modification, and a small set of conditionally exe- cuted instructions which can be useful in eliminating short conditional branches. table 2-1 is an alphabetized listing of the m?core instruction set. refer to the m?core reference manual (mcorerm/ad) for more details on instruction opera- tion. table 2-1 m?core instruction set mnemonic description abs addc addi addu and andi andn asr asrc absolute value add with c bit add immediate add unsigned logical and logical and immediate and not arithmetic shift right arithmetic shift right, update c bit bclri bf bgeni bgenr bkpt bmaski br brev bseti bsr bt btsti bit clear immediate branch on condition false bit generate immediate bit generate register breakpoint bit mask immediate branch bit reverse bit set immediate branch to subroutine branch on condition true bit test immediate
MMC2001 integer cpu motorola reference manual 2-7 clrf clrt cmphs cmplt cmplti cmpne cmpnei clear register on condition false clear register on condition true compare higher or same compare less than compare less than immediate compare not equal compare not equal immediate decf decgt declt decne dect divs divu doze decrement on condition false decrement register and set condition if result greater than zero decrement register and set condition if result less than zero decrement register and set condition if result not equal to zero decrement on condition true divide signed integer divide unsigned integer doze ff1 find first one incf inct ixh ixw increment on condition false increment on condition true index halfword index word jmp jmpi jsr jsri jump jump indirect jump to subroutine jump to subroutine indirect ld.[bhw] ldm ldq loopt lrw lsl, lsr lslc, lsrc lsli, lsri load load multiple registers load register quadrant decrement with c-bit update and branch if condition true load relative word logical shift left and right logical shift left and right, update c bit logical shift left and right by immediate mfcr mov movi movf movt mtcr mult mvc mvcv move from control register move move immediate move on condition false move on condition true move to control register multiply move c bit to register move inverted c bit to register not logical complement or logical inclusive-or rotli rsub rsubi rte rfi rotate left by immediate reverse subtract reverse subtract immediate return from exception return from interrupt table 2-1 m?core instruction set (continued) mnemonic description
motorola integer cpu MMC2001 2-8 reference manual 2.8 m?core bus interface the m?core bus is a synchronous pipelined interface. signals driven on this bus are required to meet the set up and hold time relative to the falling and rising edges of the bus clock. the m?core architecture supports byte, half-word, and word operands, allowing access to 8-,16-, and 32-bit data ports through the use of synchronous cycles con- trolled by the size outputs (tsiz0, tsiz1). m?core bus interface features are summarized below. ? 32-bit address bus with transfer size indication ? 32-bit data bus ? signals referenced to both the rising and falling edges of the bus clock ? only aligned transfers allowed ? m?core is the only bus master; no arbitration support ? 32-bit fixed port size 2.8.1 bus characteristics the bus transfers information between the m?core and external memory or a peripheral device via the external and internal bus interfaces. the m?core port size is fixed at 32 bits. external devices can accept or provide eight or 16 bits in parallel and must follow the handshake protocol described in this section. the number of bits accepted or provided during a bus transfer is defined as the transfer size. the m?core uses the address bus to specify the address for the transfer and the data bus to transfer the data. control and attribute signals indicate the beginning and type sextb sexth st.[bhw] stm stq stop subc subu subi sync sign-extend byte sign-extend halfword store store multiple registers store register quadrant stop subtract with c bit subtract subtract immediate synchronize trap tst tstnbz trap test operands test for no byte equal zero wait wait xor xsr xtrb0 xtrb1 xtrb2 xtrb3 exclusive or extended shift right extract byte 0 extract byte 1 extract byte 2 extract byte 3 zextb zexth zero-extend byte zero-extend halfword table 2-1 m?core instruction set (continued) mnemonic description
MMC2001 integer cpu motorola reference manual 2-9 of the cycle as well as the address space and size of the transfer. the selected device then controls the length of the cycle with the signal(s) used to terminate the cycle. access requests are generated in an overlapped fashion in order to support sustained single-cycle transfers. inputs to the m?core are sampled synchronously and must be stable during the sample windows defined in figure 2-4 . if an input makes a transition during the win- dow time period, the level recognized by the m?core is not predictable. outputs from the m?core change on one of the two clock edges, depending on the signal class. )ljxuh6ljqdo5hodwlrqvklsvwr&orfnv 2.8.2 bus signals figure 2-5 shows the m?core bus signals arranged by functional group. clk tsu0 th0 tsu1 th1 tsu2 th2 tsu3 th3 tsu = time set up th = time hold
motorola integer cpu MMC2001 2-10 reference manual figure 2-5 m?core bus signals 2.8.3 signal descriptions table 2-2 lists and describes the bus interface signals. more detailed descriptions can be found in subsequent sections. signal direction is relative to the m?core. addr[31:0] r/w treq tsiz[1:0] tc[2:0] ta data[31:0] tea abort 32 1 1 2 3 1 32 1 1 address and transfer attributes data transfer status termination/ tbusy 1 transfer request transfer busy lpmd[1:0] 2 power management dbgack 1 debug acknowledge
MMC2001 integer cpu motorola reference manual 2-11 2.8.4 bus operation the following sections provide a functional description of the system bus, the signals that control it, and the bus cycles provided for data transfer operations. they also describe the error conditions and reset operation. table 2-2 m?core bus signals signal name pins active i/o description address and transfer attributes addr[31:0] address bus 32 high o driven by the m?core to specify the physical address of the bus transaction. r/w read/write 1higho driven by the m?core along with the address. driven high indicates that a read access is in progress. driven low indicates that a write access is in progress. tsiz[1:0] transfer size 2higho driven by the m?core along with the address. specifies the data transfer size for the transaction. tc[2:0] transfer code 3higho driven by the m?core along with the address. indicates the type of access for the current bus cycle. transfer request/transfer busy treq transfer request 1lowo driven by the m?core along with the address and trans- fer attributes to indicate that a new access has been requested. tbusy transfer busy 1lowo driven by the m?core to indicate that an access is in progress. this signal is driven for the duration of a cycle and may be held asserted for multiple transfers. data data[31:0] data bus 32 high o driven by the m?core when it owns the bus and it initi- ated a write transaction to a slave device. eight (byte), 16 (halfword), or 32 (word) bits of data can be transferred per access. i driven by the slave in a read transaction. eight (byte), 16 (halfword), or 32 (word) bits of data can be transferred per access. transfer cycle termination and status ta transfer acknowledge 1lowi driven by the slave device to which the current transac- tion was addressed. indicates that the slave has received the data on the write cycle or returned data on the read cycle. tea transfer error acknowledge 1lowi driven by the slave device to which the current transac- tion was addressed. indicates that an error condition has occurred during the bus cycle. abort abort 1lowo driven by the m?core to indicate that the transfer is to be aborted immediately. power management lpmd[1:0] low-power modes 2lowo driven by the m?core to indicate whether the core is running in normal mode or has just executed a low power mode instruction. debug dbgack debug mode 1lowo driven by the m?core to indicate that debug mode has been entered.
motorola integer cpu MMC2001 2-12 reference manual the m?core receives a clock input (clk) from an external clock source and gener- ates two internal clocks (c1 and c2). the clk input sets the frequency of operation for the bus interface directly. the clock source monitors the m?core low power mode outputs (lpmd[1:0] ) and controls the clock input to the m?core accordingly by forcing the clocks low for low-power operation. data transfers occur between an internal register and the external bus. the internal register connects to the external data bus through the internal data bus and a data multiplexer. the data multiplexer establishes the necessary connections for different combinations of address and data sizes. this multiplexer is physically positioned in the overall system to minimize power consumption by minimizing loading and reduc- ing unnecessary signal transitions. logically, however, it is considered part of the m?core. the m?core does not support dynamic bus sizing and expects the referenced device to accept the requested access width. peripherals with an interface width of n bits should not define internal registers greater than n bits wide. misaligned transfers are not supported. the m?core interface may drive the addr[1:0] address lines to a value which is not representative of an aligned transfer, but expects aligned data to be transferred. addr[1:0] should be selectively ignored by external logic, depending on the size of the transfer. the data multiplexer takes the four bytes of the core interface data bus and routes them to their required positions to interface properly to memory or peripherals. the external multiplexer connections to memory are controlled on a byte granularity and are referred to as mb0Cmb3, where mb0 resides at byte address 0 (mod 4) and mb3 resides at byte address 3 (mod 4). for example, mb0 would normally be routed to data[31:24] on a word transfer, but it can also be routed to data[7:0] for supporting a byte data transfer. the same is true for any of the other operand bytes. figure 2-6 shows the connection requirements for the multiplexer. the transfer size (tsiz[1:0]) and byte offset (addr1 and addr0) signals determine the positioning of the bytes (see table 2-3 ). 7deoh,qwhuidfh5htxluhphqwviru5hdgdqg:ulwh&\fohv transfer size active interface bus sections mux connections tsiz1 tsiz0 addr1 addr0 data[31:24] data[23:16] data[15:8] data[7:0] byte 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 mb0 mb1 mb2 mb3 a b c d halfword 1 1 0 0 0 1 x x mb0 mb2 mb1 mb3 e f word 0 0 x x mb0 mb1 mb2 mb3 g
MMC2001 integer cpu motorola reference manual 2-13 )ljxuh([whuqdo0xowlsoh[hu&rqqhfwlrqv table 2-3 lists the combinations of the tsizx, addr1, and addr0 signals that are used for each possible transfer size and alignment. in table 2-3 , mb0Cmb3 indicate the portion of the requested operand that is read or written during that bus transfer. for word transfers, all bytes are valid as listed and correspond to portions of the requested operand. the bytes labeled with a dash are not required; they are ignored on read transfers and driven with undefined data on write transfers. 2.8.5 processor instruction/data transfers the transfer of data between the processor and other devices involves the address bus, data bus, transfer attributes, and control signals. the address and data buses are parallel, non-multiplexed buses that support aligned byte, halfword, and word transfers. all bus input and output signals are sampled or driven with respect to one of the edges of the clk signal. the m?core moves data on the bus by issuing con- trol signals and using a handshake protocol to ensure correct data movement. access requests are generated in an overlapped fashion in order to support sus- tained single-cycle transfers. once an access has been accepted, the processor is free to change the current request. access information must therefore be latched by a slave device. m?core data[31:24] data[23:16] data[15:8] data[7:0] mb0 mb1 mb2 mb3 memory port multiplexer structure (byte addr 0,4,8,c,...) (byte addr 3,7,b,f,...) (byte addr 2,6,a,e,...) (byte addr 1,5,9,d,...) g g b, e a e c f, g d, f, g connection cases
motorola integer cpu MMC2001 2-14 reference manual 2.8.6 bus exception cycles the m?core bus interface requires assertion of ta from an external device to signal that a bus cycle is complete. external circuitry can provide tea when no device responds to indicate that an error condition is associated with an access. this allows the cycle to terminate and the processor to enter exception processing for the error condition if appropriate. to control termination of a bus cycle for a bus error condition properly, ta and tea must be asserted and negated about the same rising edge of clk. the system hardware can use the tea signal to abort the current bus cycle when a fault is detected. when the processor recognizes a bus error condition for an access, the access is terminated immediately. when a bus cycle is terminated with a bus error, the m?core can enter access error exception processing immediately following the bus cycle, or it can defer processing the exception. the instruction pre-fetch mechanism requests instruction words from the instruction memory unit before it is ready to execute them. if a bus error occurs on an instruction fetch, the processor does not take the exception until it attempts to use the instruction. if an intervening instruction causes a branch or if a task switch occurs, the access error exception for the unused access does not occur. a bus error termination for any write or read access that references data specifically requested by the execution unit causes the processor to begin exception processing immediately. table 2-4 termination result summary ta tea result dont care low bus error terminate and take bus error exception if appropriate low high normal cycle terminate and continue high high insert wait states
MMC2001 system memory map motorola reference manual 3-1 section 3 system memory map 3.1 overview this section describes the address allocation conventions for the MMC2001 system. the general address map shown in table 3-1 is recommended for all members of the MMC2001 architecture. accesses to unimplemented regions of the map may result in tea termination to the processor. for the initial implementations of MMC2001, the address range of 0x4000 0000 C 0xffff ffff is reserved for future use. accesses to this range result in a transfer error termination to the cpu. note that in the current MMC2001 implementation, accesses to on-chip devices other than ram and rom are considered privileged; no user mode access is allowed to on-chip peripherals. 3.2 peripheral module address allocation the register blocks for all on-chip peripheral devices are located on 4096-byte bound- aries. peripherals that require additional address space (e.g., for buffers) are assigned additional 4-kbyte blocks. in this case, peripherals are located on a 2 n address boundary corresponding to the size of the block. within a 4-kbyte block, peripheral registers may be incompletely decoded, such that the register map repeats throughout the entire block; or the peripheral may return undefined values for unim- plemented register addresses. the description of the peripherals in this document provide information regarding the result of accesses to unimplemented registers. table 3-1 MMC2001 module address map address range use supervisor access user access 00000000 C 00000003 off-chip boot rom vector fetch (mod asserted) full 00000004 C 0fffffff on-chip rom selective 10000000 C 1fffffff on-chip peripherals none 20000000 C 2fffffff off-chip devices selective 30000000 C 3fffffff on-chip ram selective 40000000 C ffffffff reserved
motorola system memory map MMC2001 3-2 reference manual 3.3 peripheral module interface operation interface requirements for peripherals are defined to simplify the hardware interface implementation while providing a reasonable and extendable software model. the following requirements are currently defined (others may be added in the future): ? a given peripheral device appears only in the 4-kbyte region(s) allocated to it. ? for on-chip devices, registers are defined to be 16 or 32 bits wide. for registers that do not implement all 32 bits, the unimplemented bits return zero when read, and writes to unimplemented bits have no effect. in general, unimplemented bits should be written to zero to ensure future compatibility. ? all peripherals define the exact results for 32-bit, 16-bit, and 8-bit accesses. these may vary according to individual peripheral definitions. in any event, mis- aligned accesses are not supported, nor is bus sizing performed for accesses to registers smaller than the access size. 3.4 peripheral module address assignment the register maps of all peripheral devices for MMC2001 are located on 4096-byte boundaries. table 3-2 defines the address assignment for the on-chip components. table 3-2 MMC2001 address map address range (hex) use access 00000000 C 0003ffff on-chip rom array supervisor, selective user 00040000 C 000fffff rom echoes supervisor, selective user 00100000 C 0fffffff not used (access causes transfer error) 10000000 C 10000fff interrupt controller supervisor only 10001000 C 10001fff timer/reset unit supervisor only 10002000 C 10002fff not used (access causes transfer error) 10003000 C 10003fff keypad port supervisor only 10004000 C 10004fff external interface module supervisor only 10005000 C 10005fff pulse-width modulator supervisor only 10006000 C 10006fff not used (access causes transfer error) 10007000 C 10007fff gpio edge port supervisor only 10008000 C 10008fff interval spi supervisor only 10009000 C 10009fff uart 0 supervisor only 1000a000 C 1000afff uart 1 supervisor only 1000b000 C 1fffffff not used (access causes transfer error) 20000000 C 2fffffff external devices supervisor, selective user 30000000 C 30007fff on-chip ram array supervisor, selective user 30008000 C 3000ffff ram echoes supervisor, selective user 30100000 C 40000000 not used (access causes transfer error)
MMC2001 signal descriptions motorola reference manual 4-1 section 4 signal descriptions 4.1 overview this section contains brief descriptions of MMC2001 signal and power connections. specific details of signal operation are provided in the individual module descriptions. figure 4-1 shows MMC2001 signals by functional group. figure 4-1 functional signal groups kpp int[7:0] edge addr[19:0] data[15:0] clk gen xosc xtal osc/ exosc tms tdi once tdo tck txd1/tsiz0 rxd1/tsiz1 eb0 r/w oe eb1 mod clkout cpu peripheral sram test pwm clkin row[7:0] col[7:0] cts0 /pstat3 rts0 /pstat2 ispi spi_miso spi_mosi spi_en spi_clk port pwm[5:0] txd0/pstat0 rxd0/pstat1 trst de vstby vbatt cs[2:0] ,cs3 spi_gp timer/reset module rstin lvrstin rstout stby uart1 uart0 rom eim interface gasket
motorola signal descriptions MMC2001 4-2 reference manual 4.2 signal index table 4-1 pin requirements in 144-pin package name alt qty dir pull-up 1 reset 2 use external bus addr[19:0] 20 o ol address bus data[15:0] 16 i/o keeper i data bus r/w 1 o h read/write enable eb0 1 o h enable data bus byte 0 (data[15:8]) eb1 1 o h enable data bus byte 1 (data[7:0]) oe 1 o h output enable chip selects cs0 1 o cs0 chip select for external flash cs1 gpo 1 o gpoh chip select for external ram cs2 gpo 1 o gpoh chip select (spare) cs3 gpo 1 o gpol chip select for external lcd clock, reset, and miscellaneous clkin 1 i programmable clock input clkout 1 o ol programmable clock output xosc 1 o 32.768-khz xtal output exosc 1 i 32.768-khz xtal input mod 1 i boot rom control rstout 1 o resets external components rstin 1 i initiates system reset lvrstin 1 i low voltage supply switching control debug and test port control tms 1 i 47-k pull-up test mode select tdi 1 i 47-k pull-up test data input tdo 1 o test data output tck 1 i 47-k pull-up test clock input trst 1 i 47-k pull-up initiates test controller reset de 1 i/o 47-k pull-up initiates or acknowledges debug mode entry test 1 i 100-k pulldown factory test mode keypad and edge port col[7:0] gpio 8 i/o gpi column 7 C 0 row[7:0] gpio 8 i/o 47-k pull-up gpi row 7 C 0 int[7:0] gpio 8 i/o gpi external interrupts 7 C 0
MMC2001 signal descriptions motorola reference manual 4-3 uart port txd0 gpio/pstat0 1 i/o gpi rs-232 tx for ch0 or pstat0 output rxd0 gpio/pstat1 1 i/o gpi rs-232 rx for ch0 or pstat1output rts0 gpio/pstat2 1 i/o gpi rs-232 rts for ch0 or pstat2 output cts0 gpio/pstat3 1 i/o gpi rs-232 cts for ch0 or pstat3 output txd1 gpio/tsiz0 1 i/o gpi rs-232 tx for ch1 or tsiz0 output rxd1 gpio/tsiz1 1 i/o gpi rs-232 rx for ch1 or tsiz1 output ispi port spi_mosi 1 i/o master output, slave input spi_miso 1 i/o master input, slave output spi_en 1 i/o spi enable spi_clk 1 i/o spi clock spi_gp 1 o general-purpose control signal pwm port pwm[5:0] gpio 6 i/o gpi pwm inputs power supplies avdd 3 i external memory address supply agnd 3 i external memory address gnd cvdd 1 i external memory control/debug/jtag supply cgnd 1 i external memory control/debug/jtag gnd dvdd 2 i external memory data supply dgnd 2 i external memory data gnd fvdd 1 i clock/clock outputs supply fgnd 1 i clock/clock outputs gnd gvdd 2 i keypad port/interrupts supply ggnd 2 i keypad port/interrupts gnd hvdd 1 i uart/ispi supply hgnd 1 i uart/ispi gnd jvdd 1 i pwm supply jgnd 1 i pwm gnd xvdd 1 i oscillator v dd xgnd 1 i oscillator gnd vbatt 1 i standby battery supply vstby 1 i standby filter cap qvcc 4 i internal supply qvcch 4 i quiet supply high for i/o internal logic qgnd 4 i quiet gnd notes: 1. all pull-ups and pulldowns are disconnected when the pin is programmed as an output. 2. gpio = general-purpose input/output, gpo = general-purpose output, gpi = general-purpose input. table 4-1 pin requirements in 144-pin package (continued) name alt qty dir pull-up 1 reset 2 use
motorola signal descriptions MMC2001 4-4 reference manual 4.3 bus signals this section describes the interface signals for external memory and peripherals. 4.3.1 address bus (addr[19:0]) the output address bus pins are used to address external devices. to minimize power dissipation, they do not change state unless external memory is being accessed. 4.3.2 data bus (data[15:0]) these pins provide the bidirectional data bus for external memory accesses. data[15:0] are held in their previous logic state when there is no external bus activity. this is accomplished with weak keepers inside the i/o buffers. they are also kept in their previous state during hardware reset. 4.3.3 output enable (oe ) this active-low output signal indicates the bus access is a read and enables slave devices to drive the data bus. 4.3.4 read/write enable (r/w ) this active-low output signal indicates whether the current bus access is a read or write. 4.3.5 enable byte 1 (eb1 ) this active-low output pin is active during an operation to data bits data[7:0]. it may be configured to assert for both read and write cycles, or for write cycles only. 4.3.6 enable byte 0 (eb0 ) this active-low output pin is active during an operation to data bits data[15:8]. it may be configured to assert for both read and write cycles, or for write cycles only. 4.3.7 chip selects (cs3, cs[2:0] ) these output pins provide chip selects to external devices. 4.3.8 internal rom disable (mod ) this active-low input pin provides the capability of disabling the on-chip rom and forcing cs0 to be used to select an external boot rom. 4.4 exception control signals 4.4.1 reset (rstin ) this active-low input signal is used to initiate a system reset. an external reset signal resets the MMC2001 and most internal peripherals. the debug module is unaffected by rstin ; this function is provided through the trst pin.
MMC2001 signal descriptions motorola reference manual 4-5 4.4.2 low voltage reset (lvrstin ) this active-low input signal is used to initiate a system reset and to cause the backup power supply source to be selected for the ram array and the osc/time-of-day timer. this external reset signal resets the MMC2001 and most internal peripherals. the debug module is unaffected by lvrstin ; this function is provided through the trst pin. 4.4.3 reset out (rstout ) this active-low output signal is used to reset external components. this pin is asserted when any internal reset source is active. 4.5 clock signals these signals are used by the MMC2001 for controlling or generating the system clocks. see section 8 clock module and low-power modes for more information on the various clocking methods and frequencies. 4.5.1 crystal oscillator (xosc, exosc) these pins are the connections for an external crystal to the internal oscillator circuit for generation of the internal low_refclk. exosc is the input pin, and xosc is the output. 4.5.2 clock input (clkin) this input pin provides the hi_refclk clock source to the cpu and internal periph- erals. 4.5.3 clock output (clkout) this output pin provides an external clock source, either the lo_refclk or the hi_refclk. 4.6 debug and emulation support signals these signals are used for testing or serial debugging. see section 16 once? debug module for more information on these signals and debug mode. 4.6.1 test clock (tck) the test clock input (tck) pin is the test clock used to synchronize the jtag test logic. the tck pin has an internal 47-kbyte pull-up resistor. 4.6.2 test data input (tdi) the test data input (tdi) pin is the serial input for test instructions and data. tdi is sampled on the rising edge of tck and it has an internal 47-kbyte pull-up resistor.
motorola signal descriptions MMC2001 4-6 reference manual 4.6.3 test data output (tdo) the test data output (tdo) pin is the serial output for test instructions and data. tdo is three-stateable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. 4.6.4 test mode select (tms) the test mode select input (tms) pin is used to sequence the test controllers state machine. the tms is sampled on the rising edge of tck. it has an internal 47-kbyte pull-up resistor. 4.6.5 test reset (trst ) the active-low schmitt trigger input pin trst is used to initialize the test controller asynchronously. the trst pin has an internal 47-kbyte pull-up resistor. 4.6.6 debug event (de ) de is an open drain, bidirectional, active low pin. as an input, it provides a means of entering debug mode from an external command controller. as an output, it provides a means of acknowledging that the cpu has entered debug mode. this pin, when asserted as an input, causes the cpu to finish the current instruction being executed, save the instruction pipeline information, enter debug mode, and wait for commands to be entered from the serial debug input line. this pin is asserted as an output for several clock cycles when the cpu enters debug mode as a result of a debug request or as a result of meeting a breakpoint condition. if used to enter debug mode, de must be negated after the once responds with an acknowledge and before sending the first once command. the de pin has an inter- nal 47-kbyte pull-up resistor. 4.6.7 factory test mode (test) this input is used to select factory test mode. a description of the functionality of this pin is detailed in the factory test document. the test pin has an internal 100-kbyte pulldown resistor. 4.7 external interrupts/gpio signals these pins provide the software with general-purpose access external to the chip. see section 13 external interrupts/gpio (edge port) for more infor- mation on these signals. 4.7.1 external interrupts 7 C 0 (int[7:0]) these bidirectional pins comprise the external interface to the gpio module.
MMC2001 signal descriptions motorola reference manual 4-7 4.8 keypad signals 4.8.1 column strobes (col[7:0]) these are general-purpose i/o pins used as keypad column strobes. they are open- drain selectable in software. the default state at reset is general-purpose input. 4.8.2 row senses (row[7:0]) these are general-purpose i/o pins used as keypad row senses. the default state at reset is general-purpose input. on-chip 47-kbyte pull-up resistors are connected to these pins. 4.9 uart module signals the following signals are used by the uart module for data and clock signals. they are also shared for provision of internal processor status. see section 11 univer- sal asynchronous receiver/transmitter module for more information on these signals. see 7.7 eim configuration register for provision of internal status signal operation. 4.9.1 receive data (rxd0, rxd1) these signals are used for receiver data input for uart channels 0 and 1, respec- tively. data is sampled on the rising edge of the clock source, with the least significant bit received first. rxd0 is used to provide the pstat1 internal status signal when the psten bit in the eim configuration register is set. in this case it operates as an active-high pstat1 output. rxd1 is used to provide the tsiz1 internal status signal when the szen bit in the eim configuration register is set. in this case it operates as an active-high tsiz1 out- put. 4.9.2 transmit data (txd0, txd1) these signals are used for transmit data output for uart channels 0 and 1, respec- tively. the output is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loopback mode. data is shifted out at the falling edge of the clock source with the least significant bit transmitted first. txd0 is used to provide the pstat0 internal status signal when the psten bit in the eim configuration register is set. in this case it operates as an active-high pstat0 output. txd1 is used to provide the tsiz0 internal status signal when the szen bit in the eim configuration register is set. in this case it operates as an active-high tsiz0 output. 4.9.3 clear to send (cts0 ) this active-low signal can be programmed as the clear-to-send output for uart channel 0.
motorola signal descriptions MMC2001 4-8 reference manual cts0 is used to provide the pstat3 internal status signal when the psten bit in the eim configuration register is set. in this case it operates as an active-high pstat3 output. 4.9.4 request to send (rts0 ) this active-low signal can be programmed as the request-to-send input for uart channel 0. rts0 is used to provide the pstat2 internal status signal when the psten bit in the eim configuration register is set. in this case it operates as an active-high pstat2 output. 4.10 serial peripheral interface module signals the following signals are used by the serial peripheral module. see section 12 interval mode serial peripheral interface for more information on these signals. 4.10.1 spi data master out/slave in (spi_mosi) this signal is the serial data output from the spi in master mode and the serial data input in slave mode. 4.10.2 spi data master in/slave out (spi_miso) this signal is the serial data input to the ispi in master mode and the serial data out- put in slave mode. 4.10.3 spi serial clock (spi_clk) this i/o signal is the serial shift clock for the spi. 4.10.4 spi enable (spi _en) this i/o signal is the peripheral chip select pin in master mode and is a slave enable in slave mode. 4.10.5 spi general-purpose output (spi _gp) this output signal is used as a general-purpose control signal for external logic or devices. 4.11 pulse width modulator signals see section 15 pulse width modulator for more information on these sig- nals. 4.11.1 pwm[5:0] these pins provide the external interface to the pwm block. they may be configured as general-purpose i/o if the pwm output function is not needed. the default state at reset is general-purpose input.
MMC2001 signal descriptions motorola reference manual 4-9 4.12 power and ground pins these pins provide system power and ground to the MMC2001. multiple pins are pro- vided for adequate current capability. all power supply pins must have adequate bypass capacitance for high-frequency noise suppression. 4.12.1 positive supply (v dd ) this pin supplies positive power to the chip. 4.12.2 ground (gnd) this pin is the negative supply (ground) to the chip. 4.12.3 standby battery power (v batt ) this pin supplies positive battery standby power to the chip. 4.12.4 standby power filter (v stby ) this pin is used to provide an external filter capacitor connection for the standby volt- age switching logic.
motorola signal descriptions MMC2001 4-10 reference manual
MMC2001 rom module motorola reference manual 5-1 section 5 rom module 5.1 overview the rom module provides 256 kbytes of general-purpose code and data storage. 5.2 functional description the 256-kbyte rom module supports byte, halfword, and word read accesses with a 32-bit data interface to the cpu. only the requested bytes are guaranteed to be valid on accesses. write cycles that are attempted to the rom address space are termi- nated with a tea response to the cpu. the rom module base address is located at address 0x0000 0000 when the module is enabled. echoing of the rom block occurs throughout the region 0x0004 0000 C 0x000f ffff; no attempt is made to detect this condition. accesses in the range of 0x0010 0000 C 0x0fff ffff result in tea termination to the cpu. software designers should be aware that the echoing characteristics of this imple- mentation may change for future versions of the m?core family. external control is provided to disable the on-chip rom for system debugging pur- poses via a control input to the chip. when asserted, the mod input signal causes the on-chip rom to be disabled for the initial program counter fetch out of reset, and the chip select module to dedicate the cs0 output for an external boot rom. refer to section 4 signal descriptions and section 7 external interface module for details of the interaction of the mod input signal with the cs0 signal. table 5-1 rom module address map address use access 00000000 to 0003ffff rom array 00000001 to 00000003 are used as off-chip boot vectors when the mod signal is asserted supervisor, selective user 00040000 to 000fffff rom echoes on 256-kbyte boundaries supervisor, selective user 00100000 to 0fffffff not used (access causes transfer error) not applicable
motorola rom module MMC2001 5-2 reference manual the sprom control bit in the eim configuration register allows selective access pro- tection to be applied to the rom. (see 7.7 eim configuration register .) this bit may be used to control read access to the rom based on the state of the m?core psr(s) bit. attempted cycles to a protected rom address space are terminated with a tea response to the cpu. 5.3 applications the rom module can be used to store: ? reset boot code ? frequently accessed code ? table of constants ? revision and identification registers for all MMC2001 peripherals ? self-test diagnostic code
MMC2001 static ram module motorola reference manual 6-1 section 6 static ram module 6.1 overview the static ram (sram) module provides 32 kbytes of general-purpose code and data storage. 6.2 functional description the 32-kbyte sram module supports byte, halfword, and word accesses with a 32- bit data interface to the cpu. only the requested bytes are guaranteed to be valid on read accesses. the sram acknowledges all accesses to its memory space. the sram module occupies physical addresses 0x3000 0000 C 0x3000 7fff. echo- ing of the sram block occurs throughout the region 0x3000 8000 C 0x300f ffff; no attempt is made to detect this condition. accesses in the range of 0x3010 0000 C 0x3fff ffff result in tea termination to the cpu. software designers should be aware that the echoing characteristics of this imple- mentation may change for future versions of the m?core family. the spram control bit in the eim configuration register allows selective access pro- tection to be applied to the ram. (see 7.7 eim configuration register .) this bit may be used to control access to the ram based on the state of the m?core psr(s) bit. attempted cycles to a protected ram address space are terminated with a tea response to the cpu. the sram module is partitioned into two independent blocks for the purposes of bat- tery backup. an external standby power pin is provided to power both sections of the sram for data retention. the sram contents are undefined immediately following a power-on reset. table 6-1 static ram module address map address use access 30000000 to 30007fff ram array supervisor, selective user 30008000 to 3000ffff ram echoes on 32-kbyte boundaries supervisor, selective user 30100000 to 40000000 not used (access causes transfer error) not applicable
motorola static ram module MMC2001 6-2 reference manual
MMC2001 external interface module motorola reference manual 7-1 section 7 external interface module 7.1 overview the external interface module (eim) handles the interface to devices external to the MMC2001, including generation of chip selects for external peripherals and memory. it provides the following features: ? four chip selects for external devices, each covering a range of 16 mbytes ? programmable wait-state generator for each chip select ? selectable protection for each chip select ? programmable data port size for each chip select ? control for external/internal boot rom device selection ? bus watchdog counter for all bus cycles ? programmable general output capability for unused chip select outputs ? show cycles to allow internal bus cycles to be monitored externally )ljxuh(,0%orfn'ldjudp 7.2 signals 7.2.1 address bus the addr[19:0] signals are address bus outputs used to address external devices. internal bus cs0 cs1 cs2 cs3 ta , tea data[31:0] addr[31:0], r/w , tsiz, tc addr[19:0] eb[0:1] oe r/w data[15:0] mod treq , tbusy , abort mod module timer/reset eim
motorola external interface module MMC2001 7-2 reference manual 7.2.2 data bus the data[15:0] signals are bidirectional data bus pins used to transfer data between the chip and an external device. 7.2.3 read/write the r/w output signal indicates whether the current bus access is a read or write cycle. a high (logic one) level indicates a read cycle, and a low (logic zero) level indi- cates a write cycle. 7.2.4 control signals the oe and eb[0:1] signals are used to control the interface to the data bus. 7.2.4.1 output enable (oe ) this active-low output signal indicates the bus access is a read and enables slave devices to drive the data bus with read data. 7.2.4.2 enable byte 0C1 (eb[0:1] ) these active-low output pins indicate active data bytes for the current access. they can be programmed in the chip-select control registers to assert for read and write cycles or for write cycles only. eb0 corresponds to data[15:8], and eb1 corresponds to data[7:0]. 7.2.5 boot mode the mod input pin selects the initial cpu boot mode during hardware reset. if this pin is driven to a logic-low level four low_refclk clock cycles before rstout negation, then the internal rom will be disabled and the cpu will fetch the first word from offset 0x0 of the external flash memory, which is located at the abso- lute address 0x2d00000 in the cpu address space. the internal rom is disabled for the first cpu cycle only and is available for subsequent accesses. if this pin is driven to a logic-high level four low_refclk clock cycles before rstout negation, then the internal rom is enabled and the cpu fetches the first word from absolute address 0x0, which is the starting address of the internal rom. this signal is latched in the timer/reset module, and an internal version is supplied to the eim. 7.2.6 chip select outputs 7.2.6.1 chip select 0 (cs0 ) this active-low output signal is asserted based on a decode of bits addr[31:24] of the access address, and at reset based on the value of the mod input.
MMC2001 external interface module motorola reference manual 7-3 if mod is driven to a logic-low level four low_refclk clock cycles before rstout negation, and the csen0 bit is enabled (the default state on reset), then the internal rom is disabled, and cs0 is asserted for the first cpu access. the internal rom is disabled for the first cpu access only and is available for subsequent accesses. the cs0 access uses default values of 15 wait states and a 16-bit port size. 7.2.6.2 chip select 1C2 (cs[1:2] ) these active-low output signals are asserted based on a decode of bits addr[31:24] of the access address. when disabled, these pins can be used as programmable general-purpose outputs. 7.2.6.3 chip select 3 (cs3) this active-high output signal is asserted based on a decode of the internal address bus bits addr[31:24] of the access address. when disabled, this pin can be used as a programmable general-purpose output. 7.3 chip-select address range table 7-1 specifies the address range for each chip select output. 7.4 eim interface example figure 7-2 shows an example of an eim interface to memory and peripherals. table 7-1 chip select address range csenx addr[31:24] chip select typical use cleared inactive set 00101101 cs0 flash set 00101111 cs1 sram set 00101110 cs2 spare set 00101100 cs3 lcd
motorola external interface module MMC2001 7-4 reference manual figure 7-2 eim interface to memory and peripherals 7.5 eim functionality 7.5.1 configurable bus sizing the eim supports byte, halfword, and word operands, allowing access to 8- and 16- bit ports. it does not support misaligned transfers. addr[19:0] ram 128k x 8 ram 64k x 16 flash 512k x 16 addr[16:0] addr[16:0] addr[15:0] addr[16:1] addr[19:1] addr[15:0] lb ub eb0 cs0 cs3 data[15:0] data[15:0] data[15:0] data[7:0] data[7:0] addr0 e cs cs cs we we we r/w rs oe oe oe oe eim cs2 cs1 lcd control r/w oe oe eb1 r/w eb1 r/w eb1 eb0 data[7:0] r/w
MMC2001 external interface module motorola reference manual 7-5 the port size is programmable via the dsz bits in the corresponding cs control reg- ister. in addition, the portion of the data bus used for transfer to or from an 8-bit port is programmable via the same bits. an 8-bit port can reside on external data bus bits data[15:8] or data[7:0]. a word access to or from an 8-bit port requires four bus cycles to complete the trans- fer. a word access to or from a 16-bit port requires two bus cycles to complete the transfer. a halfword access to or from an 8-bit port requires two bus cycles to com- plete the transfer. in the case of a multi-cycle transfer, the lower two address bits, addr[1:0], are incremented appropriately. the eim data multiplexer takes the four bytes of the cpu interface data bus and routes them to their required positions to interface properly to memory and peripher- als. table 7-2 lists the combination of tsiz, addr[1:0] signals and dsz bits that are used for each possible transfer size, alignment, and port width. the bytes labeled with a dash are not required; they are ignored on read transfers and driven with unde- fined data on write transfers. table 7-2 interface requirements for read and write cycles transfer size signal encoding port width active interface bus sections (internal) tsiz1 tsiz0 addr1 addr0 dsz[1:0] data[31:24] data[23:16] data[15:8] data[7:0] byte 0 1 00 00 data[15:8] 01 data[7:0] 10 data[15:8] 01 00 data[15:8] 01 data[7:0] 10 data[7:0] 10 00 data[15:8] 01 data[7:0] 10 data[15:8] 11 00 data[15:8] 01 data[7:0] 10 data[7:0] halfword 1 0 0x 00 data[15:8] data[15:8] 01 data[7:0] data[7:0] 10 data[15:8] data[7:0] 1x 00 data[15:8] data[15:8] 01 data[7:0] data[7:0] 10 data[15:8] data[7:0] word 0 0 x x 00 data[15:8] data[15:8] data[15:8] data[15:8] 01 data[7:0] data[7:0] data[7:0] data[7:0] 10 data[15:8] data[7:0] data[15:8] data[7:0]
motorola external interface module MMC2001 7-6 reference manual 7.5.2 external boot rom control the mod input signal is used to determine the location of the boot rom device dur- ing hardware reset. if an external boot rom is used instead of the internal rom, the cs0 output can select the external rom coming out of reset. if mod is driven to a logic-low level four low_refclk clock cycles before rstout negation, and the csen0 bit is enabled (the default state on reset), then the internal rom is disabled, and cs0 is asserted for the first cpu cycle. the internal rom is disabled for the first cpu access only and is available for subsequent accesses. the cs0 access uses default values of 15 wait states and a 16-bit port size. if mod is driven to a logic-high level four low_refclk clock cycles before rstout negation, then the internal rom is enabled, and the cpu fetches the first word from internal rom. 7.5.3 programmable output generation unused chip select outputs can be configured to provide a programmable output sig- nal. (this functionality is not provided for the cs0 output signal. when the csen0 bit is cleared, cs0 is always inactive.) to operate as a programmable output pin, the cor- responding csenx control bit must be cleared. 7.5.4 bus watchdog operation the eim contains a bus watchdog timer that monitors the length of all requested accesses from the cpu. if an access does not terminate (i.e., the bus watchdog timer does not receive an internal ta or tea ) within 128 clocks of being initiated, the watchdog timer expires and forces the access to be terminated by asserting a tea signal to the cpu. the bus watchdog timer is automatically reset to a count of zero after the termination of each access. if an internal cpu peripheral does not terminate its access to the cpu or if the cpu accesses an unmapped location, the bus watch- dog times out to prevent the cpu from locking up. 7.5.5 error conditions the following conditions cause tea to be asserted to the cpu: ? an access to a disabled chip select (i.e., an access to a mapped chip-select address space when the csen bit in the corresponding cs control register is cleared). ? a write access to a write-protected chip-select address space (i.e., the wp bit in the corresponding cs control register is set). ? a user access to a supervisor-protected chip-select address space (i.e., the sp bit in the corresponding cs control register is set). ? bus watchdog time out when an access does not terminate within 128 clocks of being initiated. see 7.5.4 bus watchdog operation for a description of the bus watchdog operation. ? a user access to a supervisor-protected internal rom or ram (i.e., the corre- sponding sp bit in the eim configuration register is set), or user access to peripheral space.
MMC2001 external interface module motorola reference manual 7-7 7.5.6 show cycles the cpu can perform data transfers to or from internal modules without using the external bus. for debugging purposes, however, it may be desirable to have the inter- nal address and data bus appear on the external bus. these external bus cycles, called show cycles, are enabled by the shen bits in the eim configuration register. when show cycles are enabled, the eim drives the internal address bus addr[19:0] onto the external address bus pins addr[19:0]. in addition, the internal data bus sig- nals data[31:16] or data[15:0] are driven onto the external data bus pins data[15:0] according to the hdb bit in the eim configuration register. 7.6 eim programming model table 7-3 lists the registers in the eim. 7.6.1 chip-select control registers each of the external chip selects has an enable bit as well as other control attributes. the layout of the control register is slightly different for the cs0 output, which does not support the programmable output function. for cs1Ccs3 control registers, bits two to 15 (i.e., bits other than the pa and csen bits) are undefined at reset. access these registers with 32-bit loads and stores only. figure 7-3 cs0 control register table 7-3 eim memory map address use access 10004000 cs0 control register (cs0cr) supervisor only 10004004 cs1 control register (cs1cr) supervisor only 10004008 cs2 control register (cs2cr) supervisor only 1000400c cs3 control register (cs3cr) supervisor only 10004010 to 10004014 reserved supervisor only 10004018 eim configuration register (eimcr) supervisor only 10004020 to 10004fff reserved supervisor only cs0cr cs0 control register 10004000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r wsc wws edc csa oea wen ebc dsz sp wp 0 csen w reset: 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1
motorola external interface module MMC2001 7-8 reference manual x = undefined * pa reset value equals zero for cs3 and one for cs[1:2] figure 7-4 cs1 , cs2 , cs3 control registers wsc wait-state control these four bits program the number of wait states for an access to the external device connected to the chip select. table 7-4 shows the encoding of this field. when wws is cleared, setting wsc=0000 results in 1-clock transfers, wsc=0001 results in 2-clock transfers, and wsc=1111 results in 16-clock transfers. when wsc=0000, the wen and csa bits are ignored. set wsc=0000 and wws=0 for access to fast sram devices (one-clock read and write access), csa=0, wsc=0001 and wws=0 for access to normal sram (two- clock read and write access), csa=0, wsc=0001 and wws=1 for access to flash memory (two-clock read access and three-clock write access), edc, csa and wsc to the appropriate number for access to an lcd controller. cs1cr cs1 control register 10004004 cs2cr cs2 control register 10004008 cs3cr cs3 control register 1000400c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r wsc wws edc csa oea wen ebc dsz sp wp pa csen w reset: ; ; ; ; ; ; ; ; ; ; ; ; ; ;
MMC2001 external interface module motorola reference manual 7-9 wws write wait state this bit is used to determine if an additional wait state is required for write cycles. this is useful for writing to flash memories that require additional data setup time. 0 = reads and writes are the same length. 1 = an additional wait state is inserted for write cycles unless wsc is set to 1111. setting wsc to 1111 results in 16-clock transfers regardless of the wws bit. read cycles are not affected. edc extra dead cycle this bit determines whether an idle cycle is inserted after a read cycle for back-to- back external transfers to eliminate data bus contention. this is useful for slow mem- ory and peripherals. 0 = back-to-back external transfers occur normally, i.e., no idle cycle is inserted after a read cycle. 1 = an idle cycle is inserted after a read cycle for back-to-back external trans- fers, unless the next cycle is a read cycle to the same cs bank. csa chip select assert this bit is used for devices that require additional address setup time and additional address/data hold times. it determines when the chip select is asserted and whether an idle cycle is inserted between back-to-back external transfers. if wsc=0000, this bit is ignored. 0 = chip select is asserted normally, i.e., as early as possible. no idle cycle is inserted between back-to-back external transfers. 1 = chip select is asserted a clock later during both read and write cycles. in addition, an idle cycle is inserted between back-to-back external transfers. table 7-4 wait state control field settings number of wait states wsc[3:0] wws = 0 wws = 1 read access write access read access write access 00000001 00011112 00102223 00113334 01004445 01015556 01106667 01117778 10008889 1001 9 9 9 10 1010 10 10 10 11 1011 11 11 11 12 1100 12 12 12 13 1101 13 13 13 14 1110 14 14 14 15 1111 15 15 15 15
motorola external interface module MMC2001 7-10 reference manual oea oe assert this bit determines when oe is asserted during a read cycle. if wsc=0000, this bit is ignored and oe is asserted for one half of a clock cycle only. if ebc in the corre- sponding register is cleared, then the eb[0:1] outputs are similarly affected. 0 = oe is asserted normally, i.e., as early as possible. 1 = oe is asserted one half of a clock cycle later during a read cycle to this chip select address space. the cycle length and write cycles are not affected. wen eb negate this bit is used to determine when eb[0:1] outputs are negated during a write cycle. this is useful to meet data hold time requirements for slow memories. if wsc=0000, this bit is ignored and eb[0:1] outputs are asserted for one half of a clock cycle only. 0 = eb[0:1] are negated normally, i.e., as late as possible. 1 = eb[0:1] are negated one half of a clock cycle earlier during a write cycle to this chip select address space. the cycle length and read cycles are not affected. ebc enable byte control this bit is used to indicate which access types are allowed to assert the enable byte outputs (eb[0:1] ). 0 = read and write accesses are both allowed to assert the eb[0:1] outputs, thus configuring them as byte enables. 1 = only write accesses are allowed to assert the eb[0:1] outputs, thus configur- ing them as byte write enables. the eb[0:1] outputs must be configured as byte write enables for accesses to dual x8 memories. dsz data port size this field defines the width of the device data port. sp supervisor protect this bit is used to restrict accesses to the address range defined by the correspond- ing chip select if the access is attempted in the user mode of cpu operation. 0 = user mode accesses are allowed in this chip select address range. 1 = user mode accesses are prohibited. an attempted access to an address mapped by this chip select in user mode will result in a tea to the cpu and no assertion of the chip select output. 7deoh'dwd3ruw6l]h)lhog6hwwlqjv value meaning 8-bit port, resides on data[15:8] pins 8-bit port, resides on data[7:0] pins 16-bit port reserved
MMC2001 external interface module motorola reference manual 7-11 wp write protect this bit is used to restrict writes to the address range defined by the corresponding chip select. 0 = writes are allowed in this chip select address space. 1 = writes are prohibited. an attempt to write to an address mapped by this chip select will result in a tea to the cpu and no assertion of the chip select out- put. pa pin assert this bit is used to control the chip select pin when it is operating as a programmable output pin (i.e., the csen bit clear). this bit is ignored if the csen bit is set. at reset, pa bit is set for cs[1:2] and cleared for cs3. 0 = brings chip select output to logic-low level 1 = brings chip select output to logic-high level csen chip select enable this bit controls the operation of the chip select pin. 0 = chip select function is disabled. an attempted access to an address mapped by this chip select will result in tea assertion to the cpu and no assertion of the chip select output. when disabled, the pin is a general-purpose output controlled by the value of the pa control bit. when csen0 is clear, cs0 is inactive. 1 = chip select is enabled and is asserted when an access address falls within the range specified by the memory map in table 7-1 . with the exception of cs0 , this bit is cleared by reset, disabling the chip select output pin. csen0 is set at reset to allow cs0 to select from an external boot rom if mod is driven to a logic-low level four low_refclk clock cycles before rstout negation. when the chip select is enabled, the pa control bit is ignored. 7.7 eim configuration register the eim configuration register contains control bits that configure the eim and other internal blocks for certain operation modes. access this register with 32-bit loads and stores only. figure 7-5 eim configuration register eimcr eim configuration register 10004018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 szen psten sp ram sp rom hdb shen w reset: 0 0 1 1 0 0 0
motorola external interface module MMC2001 7-12 reference manual szen enable siz signal to uart ch1 pins this bit is used to select the function provided by the uart channel 1 pins. on reset, this bit is cleared. 0 = uart channel 0 operation. pins function as txd1, rxd1. 1 = siz function operation. pins function as tsiz0 and tsiz1 outputs indepen- dent of function or direction programmed in uart channel 1 control regis- ters. psten enable pstat signals to uart ch0 pins this bit is used to select the function provided by the uart channel 0 pins. on reset, this bit is cleared. 0 = uart channel 0 operation. pins function as txd0, rxd0, cts0 , and rts0 . 1 = pstat function operation. pins function as pstat outputs independent of function or direction programmed in uart channel 0 control registers. spram internal ram supervisor protect this bit is used to restrict accesses to the internal ram space if the access is attempted in the user mode of cpu operation. on reset, this bit is set. 0 = user mode accesses are allowed to the internal ram. 1 = user mode accesses are prohibited. an attempted access to the internal ram in user mode will result in tea assertion to the cpu. sprom internal rom supervisor protect this bit is used to restrict accesses to the internal rom space if the access is attempted in the user mode of cpu operation. on reset, this bit is set. 0 = user mode accesses are allowed to the internal rom. 1 = user mode accesses are prohibited. an attempted access to the internal rom in user mode will result in a tea to the cpu. hdb high data bus this bit is used to determine which byte lanes of the internal data bus are driven onto the external data bus when show cycles are enabled. this bit is ignored if shen is cleared. 0 = lower internal data bus bits data[15:0] are driven externally. 1 = upper internal data bus bits data[31:16] are driven externally. shen show cycle enable these two bits are used to determine what the eim does with the external bus during internal transfers (i.e., an access to the internal rom, ram or peripherals). when show cycles are enabled, the internal address and data bus are driven externally. on reset, show cycles are disabled.
MMC2001 external interface module motorola reference manual 7-13 7.8 external bus timing diagrams the following timing diagrams show the timing of accesses to memory or peripherals. 7deoh6krz&\foh(qdeoh)lhog6hwwlqjv value meaning show cycles disabled. the external address bus is driven with the last valid external address, and the data bus values are held by bus keepers. show cycles enabled. internal termination to the cpu during idle cycles caused by edc or csa being set follows normal operation as shown in figure 7-11 , figure 7-12 , and figure 7-13 . this means that internal transfers that occur dur- ing edc/csa idle cycles will not be visible externally. show cycles enabled. internal termination to the cpu during idle cycles caused by edc or csa being set is delayed by one clock. this ensures that all internal transfers can be externally monitored, at the expense of performance. reserved
motorola external interface module MMC2001 7-14 reference manual figure 7-6 read memory access (csa = 0, wsc = 1) mcu addr mcu r/w mcu treq cs oe , eb[0:1] data[15:0] mcu ta addr[19:0] mcu data w w s3(s1) s1 xxx xx xxx xxx xxx clk s2 addr v1 addr v2 addr v1 addr vx r r r/w oea = 1
MMC2001 external interface module motorola reference manual 7-15 figure 7-7 write memory access (csa = 0, wsc = 1, wws = 0) mcu addr mcu r/w mcu treq cs eb[0:1] data[15:0] mcu ta addr[19:0] mcu data s2 ww s3(s1) s1 x xxx xxx xxx clk addr v1 addr v2 addr vx w addr v1 w wen=1 r/w
motorola external interface module MMC2001 7-16 reference manual figure 7-8 word read access from halfword width memory mcu addr mcu r/w addr v1 mcu treq addr v1 cs s1 w w oe , eb[0:1] data[15:0] mcu ta addr v2 addr v1+2 cs1 xx addr v2 xx addr vx xx w w s5(s1) addr vy xx addr v2 xx s2 w w s2 cs2 addr[19:0] mcu data read read xxx read xxx word r xx clk halfword halfword s4 s3 addr vy xx r/w oea oea
MMC2001 external interface module motorola reference manual 7-17 )ljxuh:rug:ulwh$ffhvvwr+doizrug:lgwk0hpru\ mcu addr mcu r/w mcu treq cs s1 w w eb[0:1] data[15:0] mcu ta cs1 w s5(s1) s2 w w s2 cs2 wen addr[19:0] mcu data w wen write addr v1 addr v1 addr v2 xx addr v2 xx addr vx xx addr vy xx addr vz xx xx addr vy x write write write addr v1+2 word clk halfword halfword s3 s4 r/w
motorola external interface module MMC2001 7-18 reference manual )ljxuh:ulwhdiwhu5hdg0hpru\$ffhvv&6$ :6& ('& mcu addr mcu r/w addr v1 mcu treq addr v1 cs s1 ww oe ,eb[0:1] data[15:0] mcu ta addr vx addr v2 cs1 cs2 xx addr vy xx s3(s1) s2 addr v2 xx w s3(s1) addr vz xx addr vw xx s2 w oe , eb eb addr[19:0] mcu data x w w read write read (wsc=2, edc=0) write (wsc=1, wws=0) xx xx xx clk w w r r/w wen oea s2
MMC2001 external interface module motorola reference manual 7-19 )ljxuh:ulwhdiwhu5hdg0hpru\$ffhvv&6$ :6& ('& mcu addr mcu r/w addr v1 mcu treq addr v1 cs s1 ww oe , eb[0:1] data[15:0] mcu ta addr vx addr vy cs1 cs2 xx addr vy xx s1 s2 addr v2 xx w s3(s1) addr vz xx addr vw xx s2 w s2 oe , eb eb addr[19:0] mcu data x s3 r w r w read (wsc=1, edc=1) write (wsc=1, wws=0) xx xx clk s4 w idle wen r/w oea xx
motorola external interface module MMC2001 7-20 reference manual )ljxuh3hulskhudo5hdg$ffhvv&6$ :6& mcu addr mcu r/w mcu treq cs r/w data[7:0] mcu ta a0 mcu data s1 s2 w1 w2 w1a w2a w3 w3a w4 w4a addr x xxxxxxxxxxx read clk s1 w5 s3 w5a s4 s2 r addr x addr y oe , eb[0:1] addr y idle oea
MMC2001 external interface module motorola reference manual 7-21 figure 7-13 peripheral write access (csa = 1, wsc = 5) mcu addr mcu r/w mcu treq cs eb[0:1] data[7:0] mcu ta addr0 mcu data s1 s2 w1 w2 w1a w2a w3 w3a w4 w4a addr x clk s2 w5 s3 w5a s4 s1 addr x w w addr y addr y r/w wen idle
motorola external interface module MMC2001 7-22 reference manual )ljxuh5hdgdqg:ulwh)dvw0hpru\$ffhvv&6$ :6& ::6 mcu addr mcu r/w addr v1 mcu treq addr v1 s1 oe , eb[0:1] data[15:0] mcu ta addr v2 cs2 cs2 addr v2 xx s1 s2 s1 addr vy xx s2 s2 oe , eb eb addr[19:0] mcu data x read write read write xx clk cs read write r/w x
MMC2001 clock module and low-power modes motorola reference manual 8-1 section 8 clock module and low-power modes 8.1 overview the two clock sources to the MMC2001 are a 16.38-mhz clock input pin (hi_refclk) and a 32.768-khz crystal interface. a low-power crystal oscillator cir- cuit (osc) generates the constant crystal frequency clock low_refclk from the external 32.768 khz crystal. the cpu core is clocked by hi_refclk. peripheral modules can use the following as reference frequencies: ? the 32.768-khz low_refclk ? the 16.38-mhz hi_refclk ? a prescaled version of low_refclk ? a combination of several of the above references. the use of different clocks allows some of the peripherals to maintain a constant operational frequency even if the 16.38-mhz input signal is shut down. changing the peripheral frequency or allowing different parts of the same peripheral to use different frequencies imply rigid constraints on clock frequencies and synchronization issues which must be addressed carefully. refer to each peripheral definition for further details. in addition, the clkout pin can be driven by one of the internal clock sources (low_refclk or hi_refclk) under software control. the following table describes the clock source for each system block. table 8-1 cpu core and peripherals clock source peripheral peripheral clock source cpu core hi_refclk external interface module hi_refclk uart hi_refclk ispi hi_refclk interrupt controller hi_refclk pwm hi_refclk watchdog timer low_refclk/16384 (2 hz) time-of-day timer low_refclk/128 (256 hz) interval timer (pit) low_refclk/4 (8.192 khz) 1 notes: :khqhqdeohgdqgqrworzsrzhuglvdeohg gpio/keypad low_refclk/128 (256 hz) for interrupt debouncer jtag/once hi_refclk, tck
motorola clock module and low-power modes MMC2001 8-2 reference manual the clock module includes the following components: ? low-power oscillator for generation of low_refclk ? hi_refclk receiver and buffer ? clkout circuitry ? control circuitry for generation and gating of high frequency clocks to the cpu and peripherals ? divider circuits for generation of low frequency clocks for peripherals. a diagram of the clock module is shown in figure 8-1 .
MMC2001 clock module and low-power modes motorola reference manual 8-3 figure 8-1 MMC2001 clock module cpu_clk 32.768 khz 16.38 mhz peripherals hi_refclk low_refclk exosc xosc external vosc 32.768 khz r 4 8.192 khz r 32 256 hz por pit_running 8.192 khz * pit_clk tod_clk kpp_clk cko selector ckoe ckos clkout clkin* !stby !stby &!stop &!doze &!wait r 128 2 hz wdog_clk (to cpu, eim, interrupt controller) !stby &!stop *clkin input buffer is a special low signal swing receiver rb rs** x1 c1 c2
motorola clock module and low-power modes MMC2001 8-4 reference manual 8.2 low-power modes the MMC2001 supports the following features: ? four low-power modes: run wait doze stop ? ability to shut down all peripherals independently ? ability to shut down the clkout pin. 8.2.1 cpu core low-power modes the cpu supports four low-power modes: run, wait, doze, and stop. 8.2.1.1 run mode run mode is the normal cpu operating mode. current consumption in this mode is related directly to the frequency chosen for the hi_refclk (16.38 mhz). 8.2.1.2 wait mode wait mode is intended to be used to stop only the cpu clock until an interrupt is detected. in this mode, all peripherals continue operation and can generate inter- rupts, which cause the cpu to exit from wait mode. 8.2.1.3 doze mode doze mode affects the cpu in the same manner as wait, but with a different code on the cpu lpmd output signals, which are monitored by peripherals. each peripheral defines individual operational characteristics in doze mode. peripherals which con- tinue to run and have the capability of producing interrupts may cause the cpu to exit the doze mode and return to the run mode. peripherals which were stopped will restart operation on exit from doze mode as defined for each peripheral. 8.2.1.4 stop mode stop mode affects the cpu in the same manner as wait, but with a different code on the cpu lpmd output signals, which are monitored by peripherals. in this mode, peripherals cease operation except for the pit and watchdog timer, which may con- tinue to run (if enabled) using prescaled versions of the low_refclk clock source. the tod timer is unaffected in this mode. several sources exist to exit this mode and return to the run mode. see table 8-2 for more details. stopped peripherals stop after entering their individual reset states. when exiting stop mode, most peripherals retain their pre-stop control register values and resume operation. stop mode must be entered in a controlled manner, by shutting down each peripheral that is going to be stopped after it is ensured that its current operation is properly terminated.
MMC2001 clock module and low-power modes motorola reference manual 8-5 8.2.2 peripheral behavior in low-power modes 8.2.2.1 uart in doze mode, the uart stops activity, if so programmed, after finishing the current character transmission or reception. clocks are then shut down until the cpu exits the doze mode. when the doze mode is exited, the uart activates its internal clocks, and operation continues from the point reached before entering the doze mode. in stop mode, the uart stops immediately and freezes its operation, register values, state machines, and external pins. during the stop mode, the uart clocks are shut down. coming out of stop mode returns the uart to operation from the mode prior to stop mode entry. to avoid erroneous operation, ensure that the uart is in an idle state before stop mode is entered. 8.2.2.2 ispi in doze mode, the ispi stops activity, if so programmed, after finishing the current character transmission or reception. clocks are then shut down until the cpu exits the doze mode. when the doze mode is exited, the ispi activates its internal clocks, and operation continues from the point reached before entering the doze mode. in stop mode, the ispi stops immediately, aborts any transfer in progress, freezes its operation and register values, and forgets the state of any transfer in operation. (the state machine is reset, and the shift register is cleared.) it is assumed that when stop mode is initiated, there is some other method of shutting down external devices. dur- ing the stop mode, the ispi clocks are shut down. coming out of stop mode returns the ispi to an idle mode. to avoid erroneous operation, ensure that the ispi is in an idle state before entering the stop mode. 8.2.2.3 pwm in doze mode, the pwm channel stops activity, if so programmed, after finishing the current period. clocks are then shut down until the cpu exits the doze mode. when the doze mode is exited, the pwm channel is activated, and operation continues from the point reached before doze mode was entered. in stop mode, the pwm stops immediately and freezes its operation, register values, state machines, and external pins. during the stop mode, the pwm clocks are shut down. coming out of stop mode returns the pwm to operation from the state prior to stop mode entry. to avoid erroneous operation, ensure that the pwm is in an idle state before entering the stop mode. 8.2.2.4 interrupt controller because the interrupt controller module logic does not depend on the clock for asserting an enabled and requested interrupt to the cpu, none of the low-power modes have any influence on the modules functional behavior. the module registers will not be accessed by the cpu during the low-power mode states. once a pending
motorola clock module and low-power modes MMC2001 8-6 reference manual interrupt causes an exit from a low power mode (and therefore activation of the cpu clocks as well as the peripheral module clocks), the cpu may access the module registers to determine the interrupt source. 8.2.2.5 watchdog timer the watchdog timer uses a prescaled version of the low_refclk for its reference clock. low-power modes affect this module only if it is considered undesirable for the watchdog to time out (causing the MMC2001 to reset) when the chip is in stop or doze mode. in stop and doze mode, if so programmed, the watchdog ceases opera- tion and freezes at the current value. when exiting these modes, the watchdog resumes operation from the freeze value. it is the responsibility of software to avoid erroneous operation. 8.2.2.6 interval timer the interval timer uses a prescaled version of the low_refclk for its reference clock. in stop and doze mode, if so programmed, the pit ceases operation, and freezes at the current value. when exiting these modes, the pit resumes operation from the freeze value. it is the responsibility of software to avoid erroneous operation. 8.2.2.7 time-of-day timer the time-of-day timer module uses a prescaled version of the low_refclk for its reference clock and does not stop in any of the low power modes. 8.2.2.8 keypad port the keypad port module uses the cpu_clk for its internal operation only for cpu accesses, thus the module is not affected by the low power modes and is capable of waking up the cpu from all low power modes unless it is explicitly disabled. a pres- caled version of low_refclk is used for the debounce logic and continues to run in all modes. 8.2.2.9 peripheral state during low-power modes summary the functionality of each of the peripherals and cpu core during the various low power modes is summarized in table 8-2 . the status of each peripheral during a given mode refers to the condition the peripheral automatically assumes when the particular instruction (wait, doze, or stop) is executed. (it is possible to disable an indi- vidual peripheral by programming its dedicated control bits.) the wake-up capability field refers to the ability of an interrupt from that peripheral to force the cpu into run mode. 8.2.2.10 standby mode summary the functionality of each of the peripherals and cpu core during the standby mode is summarized in table 8-2 . standby mode is selected when the lvrstin pin is asserted. all modules except for the low-power oscillator (osc) and the time-of-day timer (tod) are held in reset in this mode. the tod continues to run.
MMC2001 clock module and low-power modes motorola reference manual 8-7 power may or may not be available to peripherals (except for the tod and osc) and cpu while in standby mode, depending on the level of v dd . the purpose of this mode is to enable the sram and tod to remain valid while the state of the other on- chip components is undefined. *dependent on programming 8.2.3 general low-power features 8.2.3.1 peripheral shut down each peripheral may be disabled by software in order to cease internal clock genera- tion and remain in a static state. each peripheral has its own specific disabling sequence (refer to each peripheral description for further details). 8.2.3.2 clkout pin shut down this output pin may be disabled in the low state to lower power consumption via the clkout enable (ckoe) bit in the reset/timer block. table 8-2 cpu core and peripherals in low-power modes module peripheral clock status during mode/wake-up capability run wait doze stop standby cpu core running stopped stopped stopped stopped uart running running/yes prog.*/yes stopped/no stopped/no ispi running running/yes prog.*/yes stopped/no stopped/no interrupt controller running stopped/yes stopped/yes stopped/yes stopped/no eim running stopped/no stopped/no stopped/no stopped/no pwms running running/yes prog.*/yes stopped/no stopped/no watchdog timer running running/yes prog.*/yes prog.*/yes stopped/no interval timer (pit) running running/yes prog.*/yes prog.*/yes stopped/no time-of-day timer (tod) running running/yes running/yes running/yes running/no gpio/keypad running running/yes running/yes stopped/yes stopped/no once running running/yes running/yes running/yes stopped/no
motorola clock module and low-power modes MMC2001 8-8 reference manual
MMC2001 timer/reset module motorola reference manual 9-1 section 9 timer/reset module 9.1 overview the timer/reset module contains the following timer submodules: the time-of-day with alarm (tod), the interval timer (pit), and the watchdog timer (wd). in addition, this module contains a reset source/chip configuration register. 9.2 timer/reset programming model table 9-1 shows the timer/reset module address map. these registers are described in the subsections that describe each submodule. table 9-1 timer/reset module address map address use access 10001000 reset source/chip configuration register (rscr) supervisor only 10001004 time-of-day control/status register (todcsr) supervisor only 10001008 time-of-day seconds register (todsr) supervisor only 1000100c time-of-day fraction register (todfr) supervisor only 10001010 time-of-day seconds alarm register (todsar) supervisor only 10001014 time-of-day fraction alarm register (todfar) supervisor only 10001018 reserved supervisor only 1000101c watchdog control register (wcr) supervisor only 10001020 watchdog service register (wsr) supervisor only 10001024 interval timer control/status register (itcsr) supervisor only 10001028 pit data register (itdr) supervisor only 1000102c pit alternate data register (itadr) supervisor only 1000102e to 10001fff reserved supervisor only 10002000 to 10002fff not used (access causes transfer error) not applicable
motorola timer/reset module MMC2001 9-2 reference manual 9.3 reset operation 9.3.1 reset pins three reset related pins are provided on MMC2001: a reset input (rstin ), a low-volt- age detect reset input (lvrstin ), and a reset output (rstout ). the rstin input is an active low input which is connected to external power-on and other reset control sources. this input is qualified as a valid reset if held low for at least four low_refclk clock cycles. the lvrstin input is an active low input which is connected to low-voltage detection circuitry. no qualification is performed for this input; it must thus be driven in a well- controlled manner. the rstout output is an active drive pin used to reset external devices. this pin is driven low when either qualified external resets are detected or on-chip resets (watchdog timer, power-up-reset circuitry) are generated. the minimum length is eight low_refclk cycles. the rstout pin remains low if either reset input pin is held low. 9.3.2 reset sources three sources are capable of generating a reset condition: ? an external qualified low condition on either reset input pin. the rstin signal must be valid low for four low_refclk clock cycles. lvrstin has no qualifi- cation requirements. ? internal watchdog timer. ? internal power-on reset circuitry. figure 9-1 reset functional block diagram low_refclk 4-cycle qual. watchdog timer 4-cycle stretcher reset status register rstin rstout to internal resets 4-cycle stretcher signal to latch mod pin power-up bypass lvrstin mod dq en internal mod signal to eim
MMC2001 timer/reset module motorola reference manual 9-3 9.3.3 reset sequence a reset sequence depends on the operational state of the chip when the reset occurs. ? an internally provided circuit detects the power-on condition and provides an immediate reset to the eight cycle stretcher input, ensuring that all the on-chip circuits are properly initialized (i.e., all the peripherals and the cpu core are in their reset state). the clkout pin is disabled. ? the reset circuit propagates the negation of the reset source and, following the stretcher delay of eight low_refclk cycles, negates the internal cpu core reset. ? after an initial power-up interval, the power-up-reset circuitry is not activated; thus an external reset trigger is first qualified for four low_refclk clock cycles before being propagated into the internal reset circuitry. it then functions with the same sequence as the power-up sequence. ? a watchdog reset is propagated immediately to the internal reset circuitry. the state of the external mod pin is latched four low_refclk cycles before the rstout pin is negated, and this state is used to control the first memory access for the initial program counter value. the memory access is from either the internal rom or external memory connected to cs0 . 9.3.4 reset source/chip configuration register (rscr) this status and control register gives the state of the reset sources and serves to control the clkout pin. writes to this register clear any previously set status bits. access this register with 32-bit loads and stores only. * = see bit description )ljxuh5hvhw6rxufh5hjlvwhu ckos clkout source this bit controls the clock source for the clkout pin. modify this pin only when the clock output has been disabled. this bit is cleared by por, a qualified assertion of the rstin pin, or a qualified assertion of the lvrstin pin. 0 = clkout source is hi_refclk 1 = clkout source is low_refclk rscr reset source/chip configuration register 10001000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0000 ckos ckoe 0000 lvrst in rst por wdr w reset: 0* 0* * * * 0*
motorola timer/reset module MMC2001 9-4 reference manual ckoe clkout enable this bit controls the drive enable for the clkout pin. it is cleared by por, a quali- fied assertion of the rstin pin, or a qualified assertion of the lvrstin pin. 0 = clkout is disabled and forced to the low state 1 = clkout is enabled and driven from the source selected by ckos lvrstin lvrstin pin this bit is set when the lvrstin pin is asserted to reset the MMC2001 chip. it is not affected by the other reset sources. when the por bit is set, however, this bit is undefined. this bit is cleared by writing to rscr. rst rstin pin this bit is set when the rstin pin is asserted and qualified by the four-cycle qualifier to reset the MMC2001 chip. it is not affected by the other reset sources. when the por bit is set, however, this bit is undefined. it is cleared by writing to rscr. por power-on reset this bit is set when an internal por occurs to reset the chip. it is not affected by the other reset sources. it is cleared by writing to rscr. wdr watchdog reset this bit is set when the watchdog timer expires. it is cleared by por, a qualified assertion of the rstin pin, a qualified assertion of the lvrstin pin, or by writing to rscr. 9.4 time-of-day timer the time-of-day timer (tod) is a free-running timer that is clocked by the crystal oscillator at a frequency of 256 hz (low_refclk/128). it is comprised of a 32-bit register which counts seconds, and another 32-bit register which holds an 8-bit frac- tion of a second, where bit 31 is 1/2 of a second and bit 24 is 1/256 of a second. the tod has an alarm function which compares the seconds and fraction registers with the seconds alarm and fraction alarm register and issues an interrupt if there is a match. figure 9-3 tod block diagram 256 hz tod fraction latch MMC2001 internal bus 1 second 32-bit tod seconds alarm 32-bit tod seconds tod fraction alarm tod fraction alarm interrupt 31 0 31 24 24 31 31 31 24 0
MMC2001 timer/reset module motorola reference manual 9-5 9.4.1 tod operation the tod seconds register (todsr) is readable and writable at any time. the tod fraction register (todfr) is always cleared to zero when the todsr is written. writes to the todfr cause the fraction register to be set to all ones, regardless of the data written. for read operations, always read the todsr before the todfr. this latches the todfr, which prevents any loss of carry information from the frac- tion to the seconds registers. the tod value is matched every 1/256 second to the alarm register if the alarm func- tion is enabled. when a match occurs, the alarm interrupt flag (aif) is set, and when the alarm interrupt enable bit (aie) is set, an interrupt is issued to the cpu. a write to the tod fraction alarm register (todfar) clears the aif. writes to the tod seconds alarm register (todsar) do not affect the clearing of the aif. the alarm match function is temporarily disabled after a write to the todsar until the todfar is written. this prevents an alarm match from occurring before the entire 40-bit alarm value is written. the tod fraction and seconds counters are undefined after a por operation and are unaffected by any other reset source. the tod alarm is disabled by any reset source. 9.4.2 tod in low-power modes the tod is unaffected by the low-power modes. an alarm interrupt may be used to exit from a low power state. 9.4.3 time-of-day control/status register (todcsr) )ljxuh72'&rqwuro6wdwxv5hjlvwhu access this register with 32-bit loads and stores only. ae alarm enable this bit controls the function of the tod alarm 0 = alarm function is off to save power 1 = alarm function is on todcsr time-of-day control/status register 10001004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 ae aie aif w reset: 0 0 0
motorola timer/reset module MMC2001 9-6 reference manual aie alarm interrupt enable this bit controls the alarm interrupt function 0 = aif is inhibited from reaching the cpu 1 = aif is allowed to request an interrupt aif alarm interrupt flag this read-only bit is the alarm interrupt flag. it is cleared by writing to the tod alarm fraction register (todfar). 0 = no alarm interrupt is present 1 = alarm interrupt is present 9.4.4 tod seconds register (todsr) the time-of-day seconds register is a 32-bit read/write register that holds the number of elapsed seconds. it is clocked by a 1-hz signal generated as a carry from the tod fraction register. when todsr is read, the content of the fraction counter is latched into a holding buffer to be read later. this prevents a fraction rollover between reads of the two registers from causing incorrect data to be read. when todsr is written, the todfr is cleared to all zeros. todsr is not affected by the watchdog reset or by a reset initiated by the external reset signal, but is undefined after a por. access this register with 32-bit loads and stores only. )ljxuh72'6hfrqgv5hjlvwhu 9.4.5 tod fraction register (todfr) the 32-bit time-of-day fraction register holds eight bits of data that represent the binary fraction of a second. it is clocked by the 32.768-khz low_refclk divided by 128 (256 hz). reads of this register return the value latched when the tod seconds register was previously read. continuous reads return the same value until the todsr is read and new data is latched from the fraction counter. these eight bits are cleared whenever the todsr is written but are not affected by either reset pin or the watchdog reset conditions. the fraction counter is undefined after a por. writes to this register cause all eight bits to be set. access this register with 32-bit accesses only. todsr time-of-day seconds register 10001008 31 0 r tod seconds register w reset: undefined on por
MMC2001 timer/reset module motorola reference manual 9-7 figure 9-6 tod fraction register 9.4.6 tod seconds alarm register (todsar) the time-of-day seconds alarm register is a 32-bit read/write register which holds data (in seconds) to be compared to the tod seconds register. the comparison is made every 1/256 of a second if the alarm function is enabled by the ae bit in the todcsr. writes to this register inhibit alarm compares until the todfar is written. for proper alarm operation, the fraction alarm register must be (re)written after a write to this register. this register is not affected by any of the reset conditions. access this register with 32-bit loads and stores only. )ljxuh72'6hfrqgv$odup5hjlvwhu 9.4.7 tod fraction alarm register (todfar) the time-of-day fraction alarm register is a 32-bit read/write register which holds eight bits of data to be compared to the tod fraction register. the comparison is made every 1/256 of a second if the alarm function is enabled by the ae bit in the todcsr. this register is not affected by any of the reset conditions. access this register with 32-bit loads and stores only. todfr tod fraction register 1000100c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r tod fraction register 0 0 0 0 0 0 0 0 w set to ones reset: undefined on por 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: todsar time-of-day seconds alarm register 10001010 31 0 r tod seconds alarm register w reset: unaffected
motorola timer/reset module MMC2001 9-8 reference manual figure 9-8 tod fraction alarm register 9.5 watchdog timer the watchdog timer is used to protect against system failures by providing a means of escape from unexpected events or programming errors. once started, the watch- dog timer must be serviced by software on a periodic basis. if servicing does not take place, the watchdog times out and asserts a reset signal. figure 9-9 watchdog timer block diagram todfar tod fraction alarm register 10001014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r tod fraction alarm register 0 0 0 0 0 0 0 0 w reset: undefined on por 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: (from clock block) reset wde (one-time write) dbug (from cpu)* wdbg (one-time write) watchdog control register (wcr) 6-bit counter underflow watchdog service register (wsr) wstp wdbg wde stop (from cpu)* wstp (one-time write) doze (from cpu)* wdze (one-time write) wdze 2 hz * note: doze and stop are generated from the cpu signals lpmd1 and lpmd0 dbug is an active high signal from the cpu indicating debug mode
MMC2001 timer/reset module motorola reference manual 9-9 9.5.1 watchdog timing specifications the watchdog timer provides time-out periods from 0.5 seconds up to 32 seconds with a time resolution of 0.5 seconds. it uses a 2-hz clock derived from a low_refclk prescaler (divide by 16384) to achieve the resolution of 0.5 seconds. the output of the prescaler circuitry is connected to the input of a 6-bit counter, result- ing in a range of 0.5 to 32 seconds. the time-out period is determined by writing the watchdog time-out field (wt) in the watchdog control register. figure 9-9 shows a block diagram of the watchdog timer. note the internal count registers are clocked using the 2-hz reference. in order to read and write these registers accurately via the cpu core (which runs from the cpu_clk), clock synchronization logic is required internal to the watchdog. this logic requires that the cpu clock frequency be greater than or equal to the low_refclk clock from which the counter clocks are derived. 9.5.2 watchdog timer after reset the watchdog is disabled by default after reset. once enabled by software, it cannot be disabled. the watchdog enable bit (wde) is located in the watchdog control regis- ter. at reset, the watchdog control register and watchdog service register are initial- ized to zero. 9.5.3 watchdog timer service operation a service sequence must be executed periodically to keep the watchdog from timing out and causing a reset. the service routine is based on writing to the watchdog ser- vice register. see 9.5.8.2 watchdog service register (wsr) . 9.5.4 watchdog timer in wait mode in wait mode, all peripheral clocks run normally. the watchdog is not affected. 9.5.5 watchdog timer in doze mode in doze mode, the watchdog may either continue to run or be halted. if the wdze (watchdog doze enable) bit is set in the watchdog control register (wcr), the watch- dog is halted. when doze mode is exited, the watchdog operation reverts to what it was prior to entering doze mode. 9.5.6 watchdog timer in stop mode in stop mode, the watchdog may either continue to run or be halted. if the wstp (watchdog stop enable) bit is set in the watchdog control register (wcr), the watch- dog is halted. when stop mode is exited, the watchdog operation reverts to what it was prior to entering stop mode.
motorola timer/reset module MMC2001 9-10 reference manual 9.5.7 watchdog timer in debug mode in debug mode, the watchdog may either continue to run or be halted. if the wdbg (watchdog debug enable) bit is set in the watchdog control register (wcr), the watchdog is halted. at this point, the timer is stopped, but register read and write accesses function normally. in this mode, the wcr one-time-write lock is disabled and the control bits can be updated. note if the wcr is updated in debug mode, it will remain updated when debug mode is exited. 9.5.8 watchdog timer programming model the watchdog programming model consists of a control register and a service regis- ter. 9.5.8.1 watchdog control register (wcr) this register contains fields that control the operation of the watchdog in different modes of operation. the write-once bits can only be written once after a reset condi- tion. subsequent attempts to write to them will not affect the data previously written. access this register with 32-bit loads and stores only. figure 9-10 watchdog control register wt watchdog time-out the six-bit wt field contains the time-out value. these bits are reloaded into the watchdog timer when it has been serviced. after reset, write wt before enabling the watchdog. the value in wt is loaded into the watchdog counter after running the ser- vice routine as well as on enabling the watchdog timer. wcr watchdog control register 1000101c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r wt 0 0 0 0 0 0 wstp wde wdbg wdze w reset: 0 0 0 0 0 0 0 0 0 0
MMC2001 timer/reset module motorola reference manual 9-11 wstp watchdog stop enable (one-time writable) 0 = watchdog not affected in stop mode 1 = watchdog disabled in stop mode wde watchdog enable (one-time writable) 0 = watchdog is disabled 1 = watchdog is enabled (once set, watchdog cannot be disabled) wdbg watchdog debug enable (one-time writable) 0 = watchdog not affected in debug mode 1 = watchdog disabled in debug mode wdze watchdog doze enable (one-time writable) 0 = watchdog not affected in doze mode 1 = watchdog disabled in doze mode 9.5.8.2 watchdog service register (wsr) when enabled, the watchdog requires that a service sequence be written to the watchdog service register (wsr). this register controls the clearing of the watchdog counter to keep it from timing out and causing a reset. if this register is not written with 0x5555 followed by 0xaaaa before the selected rate expires, the watchdog sets the wdr bit in the reset source register and asserts a system reset. both writes must occur in the order listed prior to the time-out, but any number of instructions can be executed between the two writes. access this register with 32-bit loads and stores only. figure 9-11 watchdog service register 9.6 interval timer (pit) the interval timer (pit) is a 16-bit set-and-forget timer that provides precise inter- rupts at regular intervals with minimal processor intervention. the timer can either count down from the value written in the modulus latch, or it can be a free-running down-counter. wsr watchdog service register 10001020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 0 0 0 w watchdog service register reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola timer/reset module MMC2001 9-12 reference manual figure 9-12 pit block diagram 9.6.1 pit operation the pit can be written at any time. the value written to the pit data register (itdr) determines the modulus of the timer. data read from the itdr is the present value of the modulus latch. the present counter value is read by reading the pit alternate data register (itadr). the counter is clocked at a fixed rate of 1/8192 seconds (~122 m s) which is derived from the 32.768 khz low_refclk divided by four. note the internal count registers are clocked using the above divide-by-four reference. in order to read and write these registers accurately via the cpu core (which runs from the cpu_clk), clock synchronization logic is required internal to the pit. this logic requires that the cpu clock frequency (driven from hi_refclk) be greater than or equal to the low_refclk clock that the counter clocks are derived from. figure 9-13 starting a count from an off state 9.6.2 pit as a set-and-forget timer this mode of operation is selected when the rld bit in the pit control/status register (itcsr) is set to a value of one. the counter is not directly writable from the module data bus; instead, it gets its data from the modulus latch. interrupt count = 0 16-bit modulus latch MMC2001 peripheral data bus 16-bit counter 8.192 khz load counter (low_refclk/4) 0x0005 osc osc/4 counter modulus 0x0005 0x0003 0x0004
MMC2001 timer/reset module motorola reference manual 9-13 when the counter reaches a count of zero, the pit interrupt flag (itif) is set in the itcsr and the value in the modulus latch is loaded into the counter to be decre- mented towards zero. if the pit interrupt enable (itie) bit is set in the itcsr, the interrupt flag issues an interrupt to the cpu. the counter may by directly initialized, without having to wait for the count to reach zero, when the itdr is written with the ovw bit in the itcsr set. figure 9-14 counter reloading from the modulus latch 9.6.3 pit as a free-running timer this mode of operation is selected when the rld bit in the itcsr is cleared to a value of zero. in this mode, the counter rolls over from 0x0000 to 0xffff, without reloading from the modulus latch, and continues to count. when the counter reaches a count of zero, the pit interrupt flag (itif) is set in the itcsr. if the pit interrupt enable (itie) bit is set in the itcsr, the interrupt flag can issue an interrupt to the cpu. the counter may by directly initialized, without having to wait for the count to reach zero, when the itdr is written while the ovw bit is set. figure 9-15 counter in free-running mode 9.6.4 interval timer registers the interval timer has three registers: the control/status register (itcsr), the data register (itdr), and the alternate data register (itadr). 0x0002 0x0001 0x0000 0x0005 0x0005 osc osc/4 counter modulus itif 0x0002 0x0001 0xffff 0x0005 osc osc/4 counter modulus itif 0x0000
motorola timer/reset module MMC2001 9-14 reference manual 9.6.5 pit control/status register (itcsr) figure 9-16 pit control and status register access this register with 32-bit loads and stores only. stop stop mode control this bit controls the function of the pit in stop mode 0 = pit function is not affected in stop mode 1 = pit function is frozen in stop mode doze doze mode control this bit controls the function of the pit in doze mode 0 = pit function is not affected in doze mode 1 = pit function is frozen in doze mode dbg debug mode control this bit controls the function of the pit in debug mode 0 = pit function is not affected in debug mode 1 = pit function is frozen in debug mode ovw counter overwrite enable this bit controls what happens to the counter value when the modulus latch is written. 0 = modulus latch is a holding register for values to be loaded into the counter when the count expires to zero. 1 = modulus latch is transparent. all writes to the latch will also overwrite the counter contents. itie pit interrupt enable this bit controls the pit interrupt function. 0 = itif is inhibited from reaching the cpu. 1 = itif is allowed to request an interrupt. itif pit interrupt flag this bit is the pit interrupt flag. it is cleared by writing a one to this bit or by writing to the pit data register. 0 = no pit interrupt is present 1 = pit interrupt is present itcsr interval timer control and status register 10001024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 stop doze dbg ovw itie itif rld en w reset: 0 0 0 0 0 0 0 0
MMC2001 timer/reset module motorola reference manual 9-15 rld counter reload control this bit controls whether the value contained in the modulus latch is reloaded into the counter when the counter reaches a count of zero or whether the counter rolls over from zero to 0xffff 0 = counter rolls over to 0xffff 1 = counter is reloaded from the modulus latch en pit enable this bit controls the pit enable function 0 = pit is disabled 1 = pit is enabled 9.6.6 pit data register (itdr) on a write, the data becomes the new timer modulus. this value is retained and is used at the next and all subsequent reloads until changed by another write to itdr. this value is initialized to the maximum count of 0xffff on reset. on a read, the itdr returns the value written in the modulus latch. the only way to change the value of the count directly is to preload a modulus with the ovw bit set to one. the counter value can be read from the pit alternate data register. access this register with 32-bit loads and stores only. figure 9-17 pit data register itdr pit data register 10001028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r pit data w reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
motorola timer/reset module MMC2001 9-16 reference manual 9.6.7 pit alternate data register (itadr) the pit alternate data register is a read-only register that provides access to the counter value. access this register with 32-bit loads and stores only. figure 9-18 pit alternate data register 9.6.8 pit in low-power modes the pit is unaffected by wait mode. in stop or doze mode, the timer may either con- tinue to run or be halted. if the doze or stop bit is set in the control/status register, the timer is halted in the respective mode. when doze or stop mode is exited, timer operation reverts to what it was prior to entering doze or stop mode. 9.6.9 pit in debug mode in debug mode, the module may either continue to run or be halted. if the dbg bit is set in the pit control/status register, the timer is halted. when debug mode is exited, the timer operation reverts to what it was prior to entering debug mode. itadr pit alternate data register 1000102c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r pit counter w reset:
MMC2001 interrupt controller motorola reference manual 10-1 section 10 interrupt controller 10.1 overview the interrupt controller module collects requests from multiple interrupt sources and provides an interface to the m?core interrupt control lines. the MMC2001 interrupt controller supports up to 32 interrupt sources (although not all are currently defined). the processor supports two categories of interrupts: normal and fast. the interrupt controller performs the following functions: ? indicates pending interrupt sources via a register ? independently enables/disables any interrupt source ? selects normal or fast interrupt request for any interrupt source ? provides a mechanism for software to schedule an interrupt. the interrupt controller consists of a set of control registers and associated logic to perform interrupt masking and priority support. the interrupt source register (intsrc) is a 32-bit control register with a single inter- rupt source associated with each bit. one or more interrupt lines are routed from each interrupt source to the intsrc register. this allows up to 32 distinct interrupt sources in an implementation. a corresponding 32-bit normal interrupt enable register (nier) allows individual bit masking of the intsrc register, and a normal interrupt pending register (nipnd) indicates pending normal interrupt requests. a logical and is performed on the intsrc register and the content of the nier register to form the content of the nor- mal interrupt pending (nipnd) register. a logical bit-wise or is performed on all the nipnd register bits to form the int signal routed to the cpu core. this core input sig- nal is maskable by a bit in the psr. two registers support fast interrupt requests. the fast interrupt enable register (fier) allows individual bit masking of the intsrc register, and the fast interrupt pending register (fipnd) indicates pending fast interrupt requests. a logical and is per- formed on the intsrc register and the content of the fier register to form the con- tent of the fast interrupt pending (fipnd) register. a logical bit-wise or is performed on the fipnd register bits to form the fint signal routed to the cpu core. this core input signal is maskable by a bit in the psr. these registers are readable by software. in addition, the nier and fier registers are writable. attempted writes to read-only registers are ignored. access these regis- ters with 32-bit loads and stores only.
motorola interrupt controller MMC2001 10-2 reference manual in the MMC2001, interrupt requests to the cpu are always treated as autovectored. the interrupt controller accomplishes this by asserting the cpu avec input along with the appropriate interrupt request. an interrupt handler can read the nipnd or fipnd register and then vector based on the value received. the intsrc register inputs at bit positions [0:2] are reserved for software generation of interrupts and are always forced to a one. by enabling interrupts for these bit posi- tions, software can force an interrupt request. the interrupt requests are prioritized in the following sequence: 1. fast interrupt requests 2. normal interrupt requests the two interrupt lines int and fint are mutually exclusive. if fint is asserted while int is already asserted, int is automatically negated. 10.2 interrupt controller programming model control and status registers for the interrupt controller begin at address 0x40002000. 10.2.1 interrupt source register (intsrc) access the 32-bit interrupt source register with 32-bit loads only. )ljxuh,qwhuuxsw6rxufh5hjlvwhu table 10-1 interrupt controller address map address use access 10000000 interrupt source register (intsrc) supervisor only 10000004 normal interrupt enable register (nier) supervisor only 10000008 fast interrupt enable register (fier) supervisor only 1000000c normal interrupt pending register (nipnd) supervisor only 10000010 fast interrupt pending register (fipnd) supervisor only intsrc interrupt source register 10000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 in31 in30 in29 in28 in27 in26 in25 in24 in23 in22 in21 in20 in19 in18 in17 in16 reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 in15 in14 in13 in12 in11 in10 in9 in8 in7 in6 in5 in4 in3 1 1 1 reset:
MMC2001 interrupt controller motorola reference manual 10-3 inx interrupt source x this bit indicates the state of the corresponding interrupt source. 0 = negated 1 = asserted bits [0:2] of this register are tied to logic level one to allow software to schedule inter- rupts by enabling one or more of these sources in the appropriate interrupt enable register(s) (nier, fier). 10.2.2 normal interrupt enable register (nier) access the 32-bit normal interrupt enable register with 32-bit loads and stores only. )ljxuh1rupdo,qwhuuxsw(qdeoh5hjlvwhu enx enable normal interrupt flag x this bit enables the corresponding interrupt source to request a normal interrupt. 0 = disable 1 = enable a reset operation clears this bit. when the enable flag is set and the corresponding interrupt line is asserted, the inter- rupt controller asserts a normal interrupt request. enabling an interrupt source which has an asserted request causes that interrupt to become pending, and a request to the cpu is asserted if not already outstanding. 10.2.3 fast interrupt enable register (fier) access the 32-bit fast interrupt enable register with 32-bit loads and stores only. )ljxuh)dvw,qwhuuxsw(qdeoh5hjlvwhu nier normal interrupt enable register 10000004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 en31 en30 en29 en28 en27 en26 en25 en24 en23 en22 en21 en20 en19 en18 en17 en16 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en15 en14 en13 en12 en11 en10 en9 en8 en7 en6 en5 en4 en3 en2 en1 en0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fier fast interrupt enable register 10000008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ef31 ef30 ef29 ef28 ef27 ef26 ef25 ef24 ef23 ef22 ef21 ef20 ef19 ef18 ef17 ef16 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ef15 ef14 ef13 ef12 ef11 ef10 ef9 ef8 ef7 ef6 ef5 ef4 ef3 ef2 ef1 ef0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola interrupt controller MMC2001 10-4 reference manual efx enable fast interrupt flag x this bit enables the corresponding interrupt source to request a fast interrupt. 0 = disable 1 = enable a reset operation clears this bit. when the enable flag is set and the corresponding interrupt line is asserted, the inter- rupt controller asserts a fast interrupt request. enabling an interrupt source that has an asserted request causes that interrupt to become pending, and a request to the cpu is asserted if not already outstanding. 10.2.4 normal interrupt pending register (nipnd) access the 32-bit normal interrupt pending register with 32-bit loads only. )ljxuh1rupdo,qwhuuxsw3hqglqj5hjlvwhu npx normal interrupt pending flag x this bit indicates a pending normal interrupt request from the corresponding interrupt source. 0 = no request 1 = interrupt request pending when a normal interrupt enable flag is set and the corresponding interrupt line is asserted, the interrupt controller asserts a normal interrupt request. the normal inter- rupt pending flags reflect the interrupt input lines which are asserted and are currently enabled to generate a normal interrupt. nipnd normal interrupt pending register 1000000c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 np31 np30 np29 np28 np27 np26 np25 np24 np23 np22 np21 np20 np19 np18 np17 np16 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 np15 np14 np13 np12 np11 np10 np9 np8 np7 np6 np5 np4 np3 np2 np1 np0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MMC2001 interrupt controller motorola reference manual 10-5 10.2.5 fast interrupt pending register (fipnd) access the 32-bit read-only fast interrupt pending register with 32-bit loads only. )ljxuh)dvw,qwhuuxsw3hqglqj5hjlvwhu fpx fast interrupt pending flag x this bit indicates a pending fast interrupt request from the corresponding interrupt source. 0 = no request 1 = interrupt request pending when a fast interrupt enable flag is set and the corresponding interrupt line is asserted, the interrupt controller will assert a fast interrupt request (fint cpu input). the fast interrupt pending flags reflect the interrupt input lines which are currently enabled to generate a fast interrupt and are asserted. 10.2.6 interrupt request input assignments the assignment of bits within the interrupt registers to interrupt sources is shown in table 10-2 . fipnd fast interrupt pending register 10000010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 fp31 fp30 fp29 fp28 fp27 fp26 fp25 fp24 fp23 fp22 fp21 fp20 fp19 fp18 fp17 fp16 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fp15 fp14 fp13 fp12 fp11 fp10 fp9 fp8 fp7 fp6 fp5 fp4 fp3 fp2 fp1 fp0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola interrupt controller MMC2001 10-6 reference manual table 10-2 interrupt source assignment bit number use 0, 1, 2 software 3unused 4unused 5 uart0 rts_delta 6 kpp control 7 time-of-day alarm 8pit 9unused 10 pwm0 11 pwm1 12 pwm2 13 pwm3 14 pwm4 15 pwm5 16 uart0 transmit 17 uart1 transmit 18 uart0 receive 19 uart1 receive 20 ispi 21 int0 22 int1 23 int2 24 int3 25 int4 26 int5 27 int6 28 int7 29 unused 30 unused 31 unused
MMC2001 universal asynchronous receiver/transmitter module motorola reference manual 11-1 section 11 universal asynchronous receiver/transmitter module 11.1 overview the universal asynchronous receiver/transmitter (uart) module provides asynchro- nous serial communication with external devices such as modems and other comput- ers. the uart module consists of two independent and almost identical channels. the description of a single channel in this section applies to both uart0 and uart1, with the exception of the cts and rts pin functions. these are available only for uart0. some of the key features of the uart channels are: ? full-duplex operation ? direct support of infrared data association mechanism ? robust receiver data sampling with noise filtering ? 16-entry fifos for transmit and receive ? 7- or 8-bit operation with optional even or odd parity and one or two stop bits ? generation and detection of break ? 16x bit clock generator for bit rates of 300 bps to 115.2 kbps ? three maskable interrupts ? rts interrupt with wake up from stop capability ? low-power modes the uart performs all normal operations associated with start-stop asynchronous communication. serial data is transmitted and received at standard bit rates using the internal 16x bit clock generator.
motorola universal asynchronous receiver/transmitter module MMC2001 11-2 reference manual figure 11-1 uart channel block diagram 11.2 uart signals 11.2.1 rts request to send (uart0) the rts input is used to control the transmitter. by asserting rts , the far-end device signals to the uart that it is ready to receive. when the ignore rts (irts) bit is cleared, the transmitter waits until this signal is asserted (low) before transmitting a character. this input can post an interrupt on any transition of the pin and wake up the m?core from a low power state. during a transmission when rts is negated, the uart trans- mitter completes the transmission of the current character and then shuts off. the contents of the fifo (characters to be transmitted) remain undisturbed. if the irts bit is set, the transmitter sends a character whenever a character is ready to transmit. this pin can then be used as a general-purpose input whose status is read in the rtss bit. 11.2.2 cts clear to send (uart0) this output pin serves two purposes. normally, the receiver indicates that it is ready to receive data by asserting this pin (low). when the receiver detects a pending over- run, it negates this pin. for other applications, this pin can be a general purpose out- put controlled by the cts bit in uart control register 2. cts may be programmed as a general-purpose i/o pin when the uart cts function is not being used. transmitter data path receiver data path rxd txd rts cts module interface gasket block 16x bit clock generator 16.38mhz tx fifo rx fifo peripheral gasket block data control dce interface infrared interface hi_ref_clk
MMC2001 universal asynchronous receiver/transmitter module motorola reference manual 11-3 11.2.3 txd uart transmit this pin is the transmitter serial output. in normal mode, nrz data is output. in infra- red mode, a 3/16 bit-period pulse is output for each zero bit transmitted and no pulse for each one bit transmitted. for rs-232 applications this pin must be connected to an rs-232 transmitter. txd can be programmed as a general-purpose i/o pin when the uart txd function is not being used. 11.2.4 rxd uart receive this pin is the receiver serial input. in normal mode, nrz data is expected. in infrared mode, a narrow pulse is expected for each zero bit received and no pulse for a one bit received. external circuitry must be used to convert the infrared signal to an elec- trical signal. rs-232 applications need an external rs-232 receiver to convert volt- age levels. rxd can be programmed as a general-purpose i/o pin when the uart rxd function is not being used. 11.3 sub-block description the uart contains four sub-modules. this section briefly describes the basic func- tionality of the four blocks. 11.3.1 transmitter the transmitter accepts a parallel character from the cpu and transmits it serially. the start, stop, and parity (if enabled) bits are added to the character. the transmitter posts a maskable interrupt when it is ready for parallel data. rts can be used to con- trol the flow of the serial data. if rts is negated (high), the transmitter finishes send- ing the character in progress (if any) then stops and waits for rts to again become asserted (low). a break character (continuous zeros) can be generated by the transmitter as well. for debugging purposes, parity errors can be generated. the transmitter operates from the 1x clock provided by the 16x bit clock generator. normal nrz is transmitted when the infrared interface is disabled. 11.3.2 receiver the receiver accepts a serial data stream and converts it into a parallel character. when enabled, it searches for a start bit, qualifies it, and then samples the succeed- ing data bits at the bit-center. jitter tolerance and noise immunity are provided by sampling at a 16x rate and using voting techniques to clean up the samples. once the start bit has been found, the data bits, parity bit (if parity is enabled), and stop bits are shifted in. if parity is enabled, it is checked and its status is reported in the rx register. similarly, frame errors and breaks are checked and reported. when a new character is ready to be read by the host, rx ready is asserted and an interrupt is posted (if enabled). if the receiver register is read as a 16-bit word, the interrupt is automatically cleared and the data, along with four status bits, are read by the cpu. cts can be configured as an output to indicate a pending overrun. normal nrz is expected when the infrared interface is disabled.
motorola universal asynchronous receiver/transmitter module MMC2001 11-4 reference manual 11.3.3 infrared interface the infrared interface converts data to be transmitted or received as specified in the irda serial infrared physical layer specification. for each zero to be transmitted, a narrow pulse which is 3/16 of a bit time is gener- ated. for each one to be transmitted, no pulse is generated. external circuitry must be provided to drive an infrared led. when the uart is receiving data, a narrow pulse is expected for each zero transmit- ted, and no pulse is expected for each one transmitted. circuitry external to the ic transforms the infrared signal to an electrical signal. 11.3.4 16x bit clock generator the 16x bit clock generator provides the pre-scaled bit clocks to the transmitter and receiver blocks. a divide ratio from one to 4096 may be selected in the ubrgr regis- ter. the 16x bit clock generator provides sufficient flexibility to provide almost any standard bit-clock from a variety of clock frequencies. note the baud rate error is computed as follows for 115.2 kbps: the input clock is 16.38 mhz the divide ratio selected is 9 (ubrgr[11:0] = 8) actual baud rate: 16.38 mhz/9/16 = 113.75 khz actual-required rates ratio: 115.2/113.75 = 1.0127 this results in an error-per-bit ratio of 1.27%. 11.3.5 general uart definitions the following definitions apply to both the transmitter and receiver operation: bit time the time required to serially transmit or receive one bit of data. start bit one bit time of logic zero that indicates the beginning of a data frame. a start bit must begin with a one-to-zero transition. stop bit one bit time of logic one that indicates the end of a data frame. frame a start bit, followed by a specified number of data or information bits, termi- nated by one or two stop bits. the number of data or information bits must agree between the transmitting and receiving devices. the most common frame format is one start bit followed by eight data bits (lsb first) terminated by one stop bit, for a total of ten bit times in the frame. the uart optionally provides other data formats as specified through the control registers. break a frame in which all the bits are logic zero. this includes the stop bit, which is normally a logic one, as well as the data bits. this kind of a frame is generally sent to signal the end of a message or the beginning of a new message.
MMC2001 universal asynchronous receiver/transmitter module motorola reference manual 11-5 framing error an error condition in which the stop bit of the received frame is missing. a framing error results when the frame boundaries in the received bit stream are not synchronized with the receiver bit counter. framing errors are not always detected: if a data bit in the expected stop bit time happens to be a logic one, the framing error may go undetected. a framing error is always present on the receiver side, when the transmitter is sending breaks. however, if the uart is set up to expect two stop bits, and only one is received, then this is not a framing error by defi- nition. parity error an error condition in which the calculated parity of the received data bits in the frame is different from the parity bit received on the rxd line. parity error is only calculated after an entire frame is received. overrun error an error condition in which the latest character received is ignored to prevent overwriting an already existing character in the uart receiver fifo. an overrun error indicates that the software reading the fifo is not keeping up with the actual reception of characters on the rxd line. 11.4 uart programming model this section describes the registers in the uart module. each uart channel has the following independent set of registers: ? three working registers (ucr1, ucr2, usr) that provide all status and control functions for the uart ? a separate test register (uts) for those applications that need it ? bit-rate generator register (ubrg) that controls the uart bit rate ? separate transmit and receive registers ? port control register that defines the gpio functionality of uart pins. the registers are optimized for a 16-bit bus. for example, all status bits associated with the received data are available along with the data in a single read. all register bits are readable (except tx data field in the uart transmit register), and most are read/write. all registers may be accessed either as a halfword or as a byte. the rx and tx data registers may also be accessed as 32-bit words. for these registers the upper 16 bits are forced to zeros.
motorola universal asynchronous receiver/transmitter module MMC2001 11-6 reference manual table 11-1 uart module address map address use access uart0 10009000 uart0 receive register (u0rx) supervisor only 10009002 not used supervisor only 10009004 to 1000903e u0rx echoes on word boundaries supervisor only 10009040 uart0 transmit register (u0tx) supervisor only 10009042 reserved supervisor only 10009044 to 1000907e u0tx echoes on word boundaries supervisor only 10009080 uart0 control register 1 (u0cr1) supervisor only 10009082 uart0 control register 2 (u0cr2) supervisor only 10009084 uart0 baud rate generator register (u0brgr) supervisor only 10009086 uart0 status register (u0sr) supervisor only 10009088 uart0 test register (u0tsr) supervisor only 1000908a uart0 port control register (u0pcr) supervisor only 1000908c uart0 data direction register (u0ddr) supervisor only 1000908e uart0 port data register (u0pdr) supervisor only 10009090 to 10009fff reserved supervisor only uart1 1000a000 uart1 receive register (u1rx) supervisor only 1000a002 not used supervisor only 1000a004 to 1000a03e u1rx echoes on word boundaries supervisor only 1000a040 uart1 transmit register (u1tx) supervisor only 1000a042 reserved supervisor only 1000a044 to 1000a07e u1tx echoes on word boundaries supervisor only 1000a080 uart1 control register 1 (u1cr1) supervisor only 1000a082 uart1 control register 2 (u1cr2) supervisor only 1000a084 uart1 baud rate generator register (u1brgr) supervisor only 1000a086 uart1 status register (u1sr) supervisor only 1000a088 uart1 test register (u1tsr) supervisor only 1000a08a uart1 port control register (u1pcr) supervisor only 1000a08c uart1 data direction register (u1ddr) supervisor only 1000a08e uart1 port data register (u1pdr) supervisor only 1000a088 to 1000afff reserved supervisor only 1000b000 to 1fffffff not used (access causes transfer error) not applicable
MMC2001 universal asynchronous receiver/transmitter module motorola reference manual 11-7 11.4.1 uart receive register (urx) this read-only register contains received characters and status. after reset, if the receiver is enabled (rxen = 1), the char rdy bit is zero until the first character is received, and the remainder of the register contents are undefined. the rx register is echoed to 16 word addresses in order to support unloading the fifo with the load register quadrant ( ldq ) instruction. *n = 0, 1, . . ., 15 x = undefined figure 11-2 uart receive register charrdy character ready this read-only bit indicates whether the character in the rx data field and associ- ated flags are valid and ready to be read by the host. 0 = character in rx data field and associated flags are invalid 1 = character in rx data field and associated flags valid and ready for reading at reset, this bit is cleared to zero. err error detect when set, this read-only bit indicates that the character present in the rx data field has an error status. the error can be an ovrrun, frmerr, brk or prerr. this bit is updated and valid for each received character. 0 = no error status detected 1 = error status detected at reset, this bit is cleared to zero. ovrrun receiver overrun when set, this read-only bit indicates that the receiver ignored data to prevent over- writing the data in the fifo. under normal circumstances, this bit should never be set. it indicates that the users software is not keeping up with the incoming data rate. this bit is updated and valid for each received character, and when set indicates that some number of characters were lost following the character for which the flag is set. 0 = no fifo overrun 1 = a fifo overrun was detected at reset, this bit is cleared to zero. u0rx uart0 receive register 10009000 u1rx uart1 receive register 1000a000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r char rdy err ovr run frm err brk pr err 0 0 rx data w reset: 0 x x x x x x x x x x x x x x x
motorola universal asynchronous receiver/transmitter module MMC2001 11-8 reference manual frmerr frame error when set, this read-only bit indicates that the current character had a framing error (missing stop bit). the data is possibly corrupted. this bit is updated for each charac- ter read from the fifo. every attempt is made to allow the receiver to correctly interpret data following a character marked as having a framing error. (this includes ignoring the start bit vali- dation logic, if appropriate.) however, if the transmitted data includes two stop bits, and both stop bits are incorrect, then the second stop bit will be interpreted as the start bit of the next character. 0 = character has no framing error 1 = character has a framing error at reset, this bit is cleared to zero. brk break detect when set, this read-only bit indicates that the current character was detected as a break. the data bits are all zero and the stop bit is also zero. the frame error bit is always set when this bit is set. if odd parity is selected, parity error will also be set when this bit is set. this bit is valid for each character read from the fifo. 0 = character is not a break character 1 = character is a break character at reset, this bit is cleared to zero. prerr parity error when set, this read-only bit indicates that the current character was detected with a parity error. the data is possibly corrupted. this bit is updated for each character read from the fifo. while parity is disabled, this bit always reads zero. 0 = no parity error detected for data in rx data field 1 = parity error detected for data in rx data field at reset, this bit is cleared to zero. rx data received data these read-only bits are the received character. in 7-bit mode, the msb is forced to zero. in 8-bit mode, all bits are active. 11.4.2 uart transmitter register (utx) the uart transmitter register is used by the host to write the data to be transmitted. the low byte is write-only. when this register is read, bits tx[15:8] always return zero, and tx[7:0] is not driving the bus. the tx register is echoed to 16-word addresses in order to support filling the transmit fifo with the store register quadrant ( stq ) instruction.
MMC2001 universal asynchronous receiver/transmitter module motorola reference manual 11-9 *n = 0, 1, . . ., 15 x = undefined figure 11-3 uart transmitter register tx data transmit data these write-only bits are the parallel transmit data inputs. in 7-bit mode, d7 is ignored. in 8-bit mode, all bits are used. data is transmitted lsb first. a new charac- ter is transmitted when these bits are written. these bits must be written only while trdy is high to ensure that corrupted data is not sent. 11.4.3 uart control register 1 (ucr1) uart control register 1 is a read/write register. this register enables the uart and the transmit and receive blocks. it controls the tx and rx fifo levels and enables the trdy and rrdy interrupts. figure 11-4 uart control register 1 txfl transmitter fifo interrupt trigger level these bits control the operation of the interrupt generated by the transmitter. a maskable interrupt is generated whenever the data level in the tx fifo drops below the selected threshold. the bits are encoded as follows: at reset, these bits are cleared to zero. u0tx uart0 transmitter register 10009040 u1tx uart1 transmitter register 1000a040 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 tx data reset: 0 0 0 0 0 0 0 0 x x x x x x x x u0cr1 uart0 control register 1 10009080 u1cr1 uart1 control register 1 1000a080 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r txfl trdy- en txen rxfl rrdy en rxen iren 0 rtsd en snd- brk 0 0 doze uart en w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 7deoh7[)/)lhog6hwwlqjv value meaning 00 interrupt if tx fifo has a slot for one or more character 01 interrupt if tx fifo has a slot for four or more characters 10 interrupt if tx fifo has a slot for eight or more characters 11 interrupt if tx fifo has a slot for fourteen or more characters
motorola universal asynchronous receiver/transmitter module MMC2001 11-10 reference manual trdyen transmitter ready interrupt enable setting this bit enables an interrupt when the transmitter has one or more slots avail- able in the tx fifo. the fill level in the tx fifo at which an interrupt is generated is controlled by the txfl bits. while this bit is negated, the transmitter interrupt is dis- abled. 0 = tx interrupt disabled 1 = tx interrupt enabled at reset, this bit is cleared to zero. txen transmitter enable this bit enables or disables the transmitter. while uarten and txen bits are set, and doze bit is cleared, the transmitter is enabled. if this bit is cleared in the middle of a transmission, the uart disables the transmitter immediately and starts marking ones. the transmitter fifo cannot be written to when this bit is cleared. 0 = transmitter disabled 1 = transmitter enabled at reset, this bit is cleared to zero. rxfl receiver fifo interrupt trigger level these bits control the threshold at which a maskable interrupt will be generated by the receiver. a maskable interrupt will be generated whenever the data level in the rx fifo reaches the selected threshold. at reset, these bits are cleared to zero. rrdyen receiver ready interrupt enable setting this bit enables an interrupt when the receiver has data in the rx fifo. the fill level in the rx fifo at which an interrupt is generated is controlled by the rxfl bits. clearing this bit disables rx interrupts. 0 = rx interrupt disabled 1 = rx interrupt enabled at reset, this bit is cleared to zero. rxen receiver enable setting this bit enables the receiver. when the receiver is enabled, if the rxd line is already low, the receiver does not recognize break characters, since it requires a valid one-to-zero transition before it can accept any character. 0 = receiver disabled 1 = receiver enabled at reset, this bit is cleared to zero. 7deoh5[)/)lhog6hwwlqjv value meaning 00 interrupt if rx fifo contains one or more character 01 interrupt if rx fifo contains four or more characters 10 interrupt if rx fifo contains eight or more characters 11 interrupt if rx fifo contains fourteen or more characters
MMC2001 universal asynchronous receiver/transmitter module motorola reference manual 11-11 iren infrared interface enable setting this bit enables the infrared interface. refer to 11.3.3 infrared interface . 0 = infrared interface disabled 1 = infrared interface enabled at reset, this bit is cleared to zero. rtsd en rts delta interrupt enable this bit enables or disables rts delta interrupts. the current status of the rts pin is read in the uart status register. 0 = rts interrupt disabled 1 = rts interrupt enabled at reset, this bit is cleared to zero. sndbrk send break this bit forces the transmitter to send a break character. the transmitter will finish sending the character in progress (if any) and then send break characters until this bit is reset. the user is responsible for ensuring that this bit is high for a sufficient period of time to generate a valid break; the transmitter samples sndbrk after every bit is transmitted. following completion of the break transmission, the uart transmits two mark bits. the user can continue to fill the fifo, and any characters remaining will be transmit- ted when the break is terminated. this bit cannot be changed until the uart en and tx en bits in the uart control register 1 (cr1) are set. 0 = do not send break 1 = send break (continuous zeros) at reset, this bit is cleared to zero. doze doze mode when the cpu executes a doze instruction and the system is placed in the doze mode, the doze bit affects operation of the uart. if this bit is set when the system is in the doze mode, the uart is disabled. refer to 11.7 uart operation in low- power system modes . 0 = uart unaffected in doze mode 1 = uart disabled in doze mode at reset, this bit is cleared to zero. uart en uart enable this bit enables or disables the uart. if this bit is cleared in the middle of a transmis- sion, the transmitter stops and drives the txd line to logic one. 0 = uart disabled 1 = uart enabled at reset, this bit is cleared to zero. 11.4.4 uart control register 2 (ucr2) uart control register 2 is a read/write register. this register controls the overall oper- ation of the uart. it controls the clock source, number of bits per character, parity generation and checking, and behavior of the rts , cts , and dtr pins.
motorola universal asynchronous receiver/transmitter module MMC2001 11-12 reference manual figure 11-5 uart control register 2 irts ignore rts setting this bit forces the rts input signal presented to the transmitter to always be asserted, effectively causing the external pin to be ignored. in this mode, the rts pin can be used as a general-purpose input. 0 = transmit only while rts pin is asserted 1 = ignore rts pin at reset, this bit is cleared to zero. ctsc cts pin control this bit controls the operation of the cts output pin. while this bit is set, the cts out- put pin is controlled by the receiver. when the rx fifo has a pending overrun, the cts output pin is negated to indicate to the far-end transmitter to stop transmitting. while the ctsc bit is negated, the cts output pin is controlled by the cts bit. on reset, since this bit is cleared to zero, the cts pin is controlled by the cts bit, which is also cleared to zero on reset. this means that on reset the cts signal is negated. 0 = cts pin controlled by the cts bit 1 = cts pin controlled by the receiver at reset, this bit is cleared to zero. cts cts bit this bit controls the cts pin while the ctsc bit is negated. while ctsc is asserted this bit has no function. 0 = cts pin is driven high (inactive) 1 = cts pin is driven low (active) at reset, this bit is cleared to zero. pren parity enable this bit enables or disables the parity generator in the transmitter and parity checker in the receiver. 0 = parity disabled 1 = parity enabled at reset, this bit is cleared to zero. u0cr2 uart0 control register 2 10009082 u1cr2 uart1 control register 2 1000a082 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 irts ctsc cts 0 0 0 pren proe stpb ws 0 0 0 0 0 w reset: 0 0 0 0 0 0 0
MMC2001 universal asynchronous receiver/transmitter module motorola reference manual 11-13 proe parity odd/even this bit controls the sense of the parity generator and checker. when proe is set, odd parity is generated and expected. when proe is cleared, even parity is gener- ated and expected. this bit has no function if pren is low. 0 = even parity 1 = odd parity at reset, this bit is cleared to zero. stpb stop bits this bit controls the number of stop bits transmitted after a character. when stpb is set, two stop bits are sent. when stpb is cleared, one stop bit is sent. this bit has no effect on the receiver, which expects one or more stop bits. 0 = one stop bit transmitted 1 = two stop bits transmitted at reset, this bit is cleared to zero. ws word size this bit specifies a character length of eight or seven bits (not including start, stop, or parity bits). when ws is set, the transmitter and receiver are in eight-bit mode. when ws is cleared, they are in seven-bit mode. the transmitter then ignores b7, and the receiver sets b7 to zero. this bit can be changed between transmissions or recep- tions. if it is changed while a transmission or reception is in progress, however, the length of the current character being transmitted or received is unpredictable. 0 = 7-bit transmit and receive character length 1 = 8-bit transmit and receive character length at reset, this bit is cleared to zero. 11.4.5 uart brg register (ubrgr) this register specifies the divide ratio of the prescaler in the uart bit clock genera- tor. figure 11-6 uart brg register cd clock divider these bits determine the bit clock generator output rate. the cd field is used to pre- set a 12-bit counter that is decremented at the system clock rate. the value 0x000 produces the maximum clock rate (equal to the system clock). the value 0xfff pro- duces the minimum clock rate (divide by 4096). u0brgr uart0 brg register 10009084 u1brgr uart1 brg register 1000a084 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 cd w reset: 0 0 0 0 0 0 0 0 0 0 0 0
motorola universal asynchronous receiver/transmitter module MMC2001 11-14 reference manual 11.4.6 uart status register (usr) the read/write uart status register indicates the status of the rts pin, input transi- tions on the pin, and status of the transmit and receive fifos. figure 11-7 uart status register txmpty transmitter empty when set, this bit indicates that the transmit fifo and the transmit shift register are both empty. this bit is automatically cleared when a write to the tx fifo is per- formed. 0 = tx fifo or shifter are not both empty 1 = tx fifo and shifter are both empty at reset, this bit is set to one. rtss rts pin status this bit indicates the current status of the rts pin. a snapshot of the pin is taken immediately before this bit is presented to the data bus. while irts is asserted, this bit can be used as a general-purpose input. 0 = rts pin is high (inactive) 1 = rts pin is low (active) this bit follows the logic value connected to the rts pin. trdy transmitter ready interrupt flag when set, this bit indicates that the tx fifo has emptied below its target threshold and needs data. this bit is automatically cleared when the data level in the tx fifo goes beyond the set threshold level. 0 = transmitter does not need data 1 = transmitter needs data (interrupt posted) at reset, this bit is set to one. rrdy receiver ready interrupt flag when set, this bit indicates that the receive fifo data level is above the threshold level specified by the rxfl field, and a maskable interrupt is generated. refer to the rxfl bit description for setting the threshold level. in conjunction with the charrdy bit, host software can continue to read the rx fifo in an interrupt service routine until the rx fifo is empty. this bit is automatically cleared when the data level in the rx fifo goes below the set threshold level. 0 = no character ready (no interrupt posted) 1 = character(s) ready (interrupt posted) at reset, this bit is cleared to zero. u0sr uart0 status register 10009086 u1sr uart1 status register 1000a086 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r tx mpty rtss trdy 0 0 0 rrdy 0 0 0 rtsd 0 0 0 0 0 w reset: 1 0 1 0 0
MMC2001 universal asynchronous receiver/transmitter module motorola reference manual 11-15 rtsd rts delta when set, this bit indicates that the rts pin changed state. it generates a maskable interrupt. in stop mode, rts assertion sets this bit to wake the cpu. the current state of the rts pin is available in the rtss bit. the rtsd interrupt is cleared by writing a one to this bit. 0 = rts pin did not change state since last cleared 1 = rts pin changed state at reset, this bit is cleared to zero. 11.4.7 uart test register (uts) the uart test register is a read/write register. unimplemented bits always return zero when read. this register contains miscellaneous bits to control test features of the uart block. figure 11-8 uart test register frc perr force parity error when set, this bit forces the transmitter to generate a parity error if parity is enabled. this bit is provided for system debugging. 0 = generate normal parity 1 = generate inverted parity (error) at reset, this bit is cleared to zero. loop loop tx and rx for test this bit controls loopback for test purposes. while this bit is high, the receiver input is internally connected to the transmitter and ignores the rxd pin. the transmitter is unaffected by this bit. this loopback operates to connect the data on the txd pin directly to the voting logic. if infrared mode is enabled (ir_en is active), the effect of activating this bit is to put an ir-formatted bit stream into the voting logic, which will yield odd results. do not use this loopback if ir_en is active. 0 = normal receiver operation 1 = internal connect transmitter output to receiver input at reset, this bit is cleared to zero. loop ir loop tx and rx for ir test this bit controls a loopback from transmitter to receiver in the infrared interface. 0 = no ir loop 1 = connect ir transmit to ir receiver at reset, this bit is cleared to zero. u0ts uart0 test register 10009088 u1ts uart1 test register 1000a088 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 frc perr loop 0 loop ir 0 000000000 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola universal asynchronous receiver/transmitter module MMC2001 11-16 reference manual 11.5 gpio pins and registers the gpio functionality of uart pins is controlled by three registers: the port control register (upcr), data direction register (uddr), and port data register (updr). 11.5.1 uart port control register (upcr) the read/write uart port control register controls the functionality of uart gpio pins. figure 11-9 uart port control register pcx port control bit x 0 = corresponding pin is configured as gpio pin 1 = corresponding pin is configured as uart pin at reset, these bits are cleared to zero. 11.5.2 uart data direction register (uddr) the read/write uart data direction register controls the direction of uart gpio pins. figure 11-10 uart data direction register table 11-4 uart pins gpio assignment gpio bit uart pin p0 rxd p1 txd p2 rts p3 cts u0pcr uart0 port control register 1000908a u1pcr uart1 port control register 1000a08a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 00000 pc3 pc2 pc1 pc0 w reset: 0 0 0 0 u0ddr uart0 data direction register 1000908c u1ddr uart1 data direction register 1000a08c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 00000 pdc3 pdc2 pdc1 pdc0 w reset: 0 0 0 0
MMC2001 universal asynchronous receiver/transmitter module motorola reference manual 11-17 pdcx port direction control bit x 0 = corresponding gpio pin is configured as input 1 = corresponding gpio pin is configured as output at reset, these bits are cleared to zero. 11.5.3 uart port data register (updr) the uart port data register is used to read or write data to or from uart gpio pins. x = undefined figure 11-11 uart port data register pdx port data bit x these bits are used to read or write data from/to the corresponding port pins if they are configured as gpio (by pc[3:0] bits in upcr). if a port pin x is configured as a gpio input, then the corresponding pdx bit will reflect the value present on this pin. if a port pin x is configured as a gpio output, then the value written into the corre- sponding pdx bit will be reflected on the pin. note that since the cts and rts pins are not present for uart1, the corresponding port control register bits should be configured in a manner which provides determinis- tic data when the port data register is read. one method for doing so is to configure the missing pins as general-purpose outputs. 11.6 data sampling technique on the receiver the uart receiver is responsible for synchronization to the serial data stream and recovery of data characters. since the data stream has no clock, data recovery depends on the transmitting device and the receiving device operating at close to the same bit rate. the uart system can tolerate a moderate amount of system noise without losing any information. the uart receive function is somewhat more difficult than the transmit function due to the asynchronous nature of incoming serial data. a discussion of the way the uart recognizes a start bit follows. the receiver front-end logic uses a sampling clock that is 16 times the bit rate. this sampling clock is called the rt clock in the following discussion, and one rt is understood to be one-sixteenth of a bit-time. in the following figures, the rt clock cycles are numbered from one (start of a bit time) to sixteen (end of a bit time). u0pdr uart0 port data register 1000908e u1pdr uart1 port data register 1000a08e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 00000 pd3 pd2 pd1 pd0 w reset: x x x x
motorola universal asynchronous receiver/transmitter module MMC2001 11-18 reference manual when the receiver is first enabled and after the reception of a stop bit at the end of a frame, an asynchronous search is initiated to find the leading edge of the next start bit. (in the case of a framing error, because the stop bit has been somehow cor- rupted, the start-bit validation logic may not operate (because there may not be a negative edge to detect). as long as the voting logic is able to detect a start bit, the receiver will be able to continue receiving characters following a framing error.) the goal of this asynchronous search is to gain bit-time synchronization between the serial data stream and the internal rt clock. once synchronization has been estab- lished, the rt clock controls where the uart perceives the bit-time boundaries to be. the first step in locating a start bit is to find a sample where rxd is zero preceded by four consecutive samples of logic ones. these five samples are called start-bit qualifiers. until the start-bit qualifiers are detected, the rt clock is reset to state rt1 after each sample. once the qualifiers are found, the beginning of a start bit is tentatively assumed, and successive samples are assigned successive rt state numbers. the next six sam- ples are taken as start-bit verification samples. if even one of these is a logic one, the low at rt1 is assumed to have been noise, and the asynchronous search is started again. when the start-bit qualifiers and the start-bit verification requirements are met, synchronization has been achieved, and the rt count state is used to determine the position of bit-time boundaries. during each bit time, including the start and stop bit times, data samples are taken to determine the logic sense of the bit time. the samples are taken at rt9, rt10, and rt11 or at rt8, rt9, and rt10, depending upon the synchronization of the incoming data. the logic sense of the bit time is considered to be the majority of the three sam- ples under consideration. at the end of a character reception, data is transferred from the shift register to the parallel receiver register, with the corresponding flags updated in the receiver register and the status register.
MMC2001 universal asynchronous receiver/transmitter module motorola reference manual 11-19 figure 11-12 start bit ideal case figure 11-12 shows the details of the ideal case of start-bit recognition. all samples taken at [1] detect logic ones on the rxd line and correspond to the idle-line time or a stop-bit time prior to this start bit. at [2] a logic zero sample is preceded by four logic one samples. these five samples are the start-bit qualifiers. the beginning of the start bit time is tentatively perceived to occur between the fourth logic one sample and the logic zero sample of the start qualifiers. next, the samples at rt2, rt3, rt4, rt5, rt6, and rt7 [3] are taken to verify that this bit time is indeed the start bit. the samples at rt8, rt9, and rt10 (or rt9, rt10, and rt11) are called the data sam- ples [4]. these samples drive a majority voting circuit to determine the logic sense of the bit time. in this ideal case, the actual start bit and the perceived start bit match. the resolution of the rt clock leads to an uncertainty about the exact placement of the leading edge of the start bit. the uncertainty in the placement of the edge will be one-sixteenth of a bit-time. rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt4 rt5 rt6 rt7 rt8 rt9 rt3 rt10 rt11 rt12 rt13 rt14 rt15 rt16 rt1 rt2 rt3 rt4 rt5 rt6 rt7 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 rxd pin samples rt clk (16x bit rate) rt clk state reset rt actual start bit perceived start bit lsb [1] [2] [3] [4]
motorola universal asynchronous receiver/transmitter module MMC2001 11-20 reference manual figure 11-13 start bit noise case one figure 11-13 shows what occurs if noise causes a sample to be erroneously detected as a zero before the actual beginning of the start bit. the logic zero sample [1] in conjunction with the four preceding samples of logic one meet the conditions for start qualification; thus, logic tentatively perceives the start bit as beginning here. subsequent start-verification samples at rt2, rt3, rt4, rt5, rt6, and rt7 [2] are not all logic zeros; therefore, the tentative placement of the start edge is rejected, and the search is restarted. when the sample at the actual beginning of the start bit is detected, the preceding three samples are ones; the start bit is now perceived to begin here. in this case, the three samples taken at rt2, rt3, rt4, rt5, rt6, and rt7 [3] now verify that the start bit has been found. if the noise bit [1] is further away from the beginning of the actual start bit, the perceived start bit will still be correct. rt1 rt1 rt1 rt1 rt1 rt2 rt4 rt5 rt6 rt7 rt8 rt9 rt3 rt10 rt11 rt12 rt13 rt14 rt15 rt16 rt1 rt2 rt3 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 rxd pin samples rt clk (16x bit rate) rt clk state reset rt actual start bit perceived start bit lsb [1] [2] rt4 rt5 rt6 rt7 rt1 [3]
MMC2001 universal asynchronous receiver/transmitter module motorola reference manual 11-21 figure 11-14 start bit noise case two figure 11-14 is similar to the previous case except noise [1] is now closer to the actual beginning of the start bit. the noise sample and the preceding four logic ones meet the start qualification requirements. the start verification samples at rt2, rt3, rt4, rt5, rt6, and rt7 [2] are not all zeros; therefore, the tentative placement of the start edge is rejected, and the search for the start qualifiers is restarted at [3]. since there are no more cases of four logic ones in a row [3], the start bit is never detected. because the circuit could not locate the start bit, the frame will be received as a framing error, improperly received, or missed entirely, depending on the data in the frame and when the start logic synchronized on what it thought was a start bit. this causes incorrect data reception. rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt6 rt7 rt1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rxd pin samples rt clk (16x bit rate) rt clk state reset rt actual start bit no start bit found lsb [1] [2] rt1 rt1 rt1 rt1 rt1 [3]
motorola universal asynchronous receiver/transmitter module MMC2001 11-22 reference manual figure 11-15 start bit noise case three figure 11-15 illustrates the case where the start edge is qualified by the four logic ones followed by a logic zero [1]. a burst of noise is present in the middle of the start bit time. the noise [3] causes two out of the three data samples to be erroneously detected as logic ones. this is rejected, therefore, as a start bit, because the majority of samples rt8, rt9, and rt10 [3] suggest it should be a logic one. rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt4 rt5 rt6 rt7 rt8 rt9 rt3 rt10 rt11 rt12 rt13 rt14 rt15 rt16 rt1 rt2 rt3 rt4 rt5 rt6 rt7 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 rxd pin samples rt clk (16x bit rate) rt clk state reset rt actual start bit no start bit found lsb [1] [2] [3]
MMC2001 universal asynchronous receiver/transmitter module motorola reference manual 11-23 figure 11-16 start bit noise case four the case depicted in figure 11-16 is similar to the previous case. in this case the start bit is not detected. the frame will be lost or in error, depending on the data in the actual frame and when the start logic got synchronized. in this case, [1] qualifies the start edge. however, the samples in [2] are not all logic zero due to the presence of noise which causes the sample rt7 to be erroneously read as logic one. thus, the tentative start edge is rejected and the search for the start edge qualifier is started once again. this happens even though all the data samples in the start bit [3] were logic zero. if this were anything but a start bit, the voting logic would have taken the right decision. 11.7 uart operation in low-power system modes the uart serial interface operates as long as the 16x bit clock generator is provided with the system clock. the peripheral interface is operational while the cpu_clk is running. the three bits rxen, txen and uart en, set by the user, give the capabil- ity to control low-power modes through software. table 11-5 shows uart functional- ity while in hardware controlled low-power modes. table 11-5 uart low-power mode operation normal mode wait mode doze mode stop mode doze = 0 doze = 1 system clock on on on off off uart serial interface on on on off off module interface on on on off off rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt4 rt5 rt6 rt7 rt1 rt1 rt3 rt1 rt1 rt1 rt1 rt1 rt1 rt1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 rxd pin samples rt clk (16x bit rate) rt clk state reset rt actual start bit no start bit found lsb [1] [2] [3]
motorola universal asynchronous receiver/transmitter module MMC2001 11-24 reference manual in doze mode, the uart behavior depends on the doze control bit. while the doze bit is cleared, the uart serial interface is unaffected. while the system is in doze mode, and the doze bit is set, the uart is disabled. if the doze mode is entered with the doze bit set while the uart serial interface was receiving or transmitting data, it will finish receiving or transmitting the current character and signal to the far- end transmitter or receiver to stop sending or receiving. there is no guarantee that the data currently present in the receiver and transmitter fifos will not be corrupted. 11.8 uart operation in system debug mode in debug mode, reads of the uart receiver register do not cause the rx fifo to bump. that is, the value at the read side of the rx fifo does not change as a result of reading this register in debug mode. repeated reads of the uart receiver register, therefore, do not cause its value to change once it contains a valid character.
MMC2001 interval mode serial peripheral interface motorola reference manual 12-1 section 12 interval mode serial peripheral interface the interval mode serial peripheral interface (ispi) module provides a high-speed synchronous serial interface to communicate to external devices such as a/d con- verters and non-volatile rams. the ispi provides the control and clock for data trans- fers and can be configured as either a master or a slave device. in addition, the ispi includes a timer that delays the initiation of a serial transfer for a programmable period. 12.1 overview the ispi transfers data between the MMC2001 and a peripheral device over a serial link. enable and clock signals are used to exchange data between the two devices. if the external device is a transmit-only device (e.g., an a/d converter), the ispi output port can be ignored or used for other purposes. figure 12-1 shows a block diagram of the ispi. figure 12-1 ispi channel block diagram 12.2 operation the ispi provides three operating modes. manual mode is a traditional spi master operation mode. interval mode is similar to manual mode, except that it includes a programmable timer to support timed transfers. interval mode is suitable for control- ling an external sound dac, for example. spi_clk spi_miso spi_mosi module spi_en spi_gp spi_irq ispi interval bit baud state control tx rx shift interface
motorola interval mode serial peripheral interface MMC2001 12-2 reference manual in slave mode, the ispi operates as a traditional slave spi; the clock becomes an input, and the transfer is controlled entirely by the external master device. figure 12-2 timing diagram of ispi 8-bit operation the ispi supports clocked transfers of all variations of phase and polarity by control- ling spi_clk (see figure 12-2 ). under normal phase (pha=0), data is latched with the leading edge of spi_clk, and data changes with the trailing edge of spi_clk. for normal phase, the leading edge is rising if pol=0, and is falling if pol=1. under opposite phase (pha=1), data changes on the leading edge of spi_clk and is latched on the trailing edge. for opposite phase, the leading edge is rising if pol=0 and is falling if pol=1. this flexibility allows operation with most serial peripheral devices on the market. 12.2.1 manual (master) mode when a data exchange is needed, the user sets the spi_en bit in the ispi control register. control values such as the number of transfer clocks, polarity, and phase are also loaded into the ispi control register. the transfer is initiated by writing the ispi tx data register. during the transfer, data in the shift register is exchanged with data in the peripheral. setting the irq_en bit enables the posting of an interrupt upon completion of the transfer. the user then negates the spi_en register bit to complete the operation. for systems that need more than 16 clocks to transfer data, the spi_en bit can remain set between exchanges. spi_clk spi_en spi_in (pha=0, pol=0) b7 b6 b5 b4 b3 b2 b1 b0 spi_out b7 b6 b5 b4 b3 b2 b1 b0 spi_clk spi_clk spi_clk (pha=1, pol=1) (pha=0, pol=1) (pha=1, pol=0) (sns=0) note: spi_in and spi_out can appear on either spi_mosi and spi_miso, depending on the mode selected by the mstr bit.
MMC2001 interval mode serial peripheral interface motorola reference manual 12-3 12.2.2 interval (master) mode interval mode provides the user with the ability to exchange data at programmed peri- odic intervals. this rate is controlled by three counters: the bit counter, the baud counter, and the ispi interval timer. this mode begins operation as soon as the ivl_en bit is set in the ispi control register. (if a transfer is in progress, then opera- tion begins upon completion of the existing transfer.) in interval mode (in contrast to manual mode), the spi_en pin is active only when a transfer is in progress; that is, in interval mode the state machine controls the enable pin. the spi_en enable bit (bit 12) must still be set in the ispi control register. an interval begins with the loading of the actual ispi interval timer. once this decre- menting counter reaches zero, the state machine begins the data transfer. when the transfer is completed, an interrupt is generated (if enabled by irq_en), and the inter- val is completed. at this point the ispi automatically begins another interval by reloading the interval timer. the length of an interval is governed by the following equation: time_of_interval = (hi_refclk_period * 2 * (interval_count+2)) + (hi_refclk_period * baud_count * (clock_count+1)) 12.2.3 slave mode in slave mode, data exchanges are controlled by external devices through the pins spi_clk and spi_en. if pin spi_en is enabled (low), then data is latched into the shift register on every other edge of spi_clk; the latching edge is determined by the pol and pha bits in the ispi control register. data is transferred from the shift regis- ter to the ispi (rx) data register when pin spi_en becomes inactive, or when the bit counter times out. in addition, irq is set at that time (if permitted by irq_en). if the rx data register is not unloaded prior to a new reload, the ovr (ispi overrun) bit is set in the ispi status register, and the data is overwritten, causing prior received data to be lost. spi_clk must not exceed hi_refclk/16. 12.3 signal descriptions 12.3.1 spi_miso (master in, slave out) in either master mode, this pin is the input to the shift register. a new bit is shifted in on each leading edge of spi_clk in normal clock mode or on each trailing edge of spi_clk in inverted clock mode. in slave mode, this pin is the output of the shift reg- ister. a new data bit is presented on each trailing edge of the spi_clk in normal clock mode (pha=0). as a slave mode output, spi_miso is three-stated when the spi_en input is negated.
motorola interval mode serial peripheral interface MMC2001 12-4 reference manual 12.3.2 spi_mosi (master out, slave in) in slave mode, this pin is the input to the shift register. a new bit is shifted in on each leading edge of spi_clk in normal clock mode or on each trailing edge of spi_clk in inverted clock mode. in either master mode, this pin is the output of the shift regis- ter. a new data bit is presented on each falling edge of the spi_clk in normal clock mode (pha=0, pol=0). 12.3.3 spi_en in manual mode, this pin is directly controlled by the spi_en bit in the ispi control register (bit 12), and can be used as a general-purpose output as well as for enabling an external device. in interval mode, its control is gated by the state machine. as an input (in slave mode), spi_en is active low. as an output (in master modes), the active sense is determined by the value of bit sns in the ispi control register. 12.3.4 spi_clk this pin is the clock output in manual or interval mode. when the ispi is enabled, a selectable number of clock pulses are issued. in slave mode, this pin is an input but controls spi operation just as it does in the two master modes. in slave mode, spi_clk must not exceed hi_refclk/16. 12.3.5 spi_gp this output pin is a general-purpose output which can be used as a control signal to a selected external device. the value driven out is controlled by the spigp bit in the ispi control register. 12.4 ispi programming model these registers control the operation of the ispi and report its status. the data regis- ter exchanges data with external slave devices. after reset, all bits are cleared. these registers should be accessed with halfword accesses. accesses other than halfword in size result in undefined activity. table 12-1 ispi module address map address use access 10008000 ispi send/receive data register (spdr) supervisor only 10008002 ispi control register (spcr) supervisor only 10008004 ispi interval control register (spicr) supervisor only 10008006 ispi status register (spsr) supervisor only 10008008 to 10008fff reserved supervisor only
MMC2001 interval mode serial peripheral interface motorola reference manual 12-5 12.4.1 ispi data register the ispi data register (spdr) contains data to be exchanged with external devices. either writing or reading this register clears any set interrupt. figure 12-3 ispi data register rx data receive data this read-only register contains the data bits received from the shift register. those bits more significant than the size determined in clock count (ispi control regis- ter) return zeros when read. for example, if clock count = 0x8 (9-bit transfer), then bits 15 to 9 are forced to zeros. the value in this register is updated at the end of every transfer. tx data transmit data this write-only register contains the data bits to be transmitted to the external device. data is copied from this register to the shift register at the time that the xch bit is set. as data is shifted msb first, outgoing data is msb-justified relative to the clock count field in the ispi control register. for example, if the exchange length is ten bits (clock count = 0x9), the msb of the outgoing data is bit nine. the first bit presented to the external device is bit 9, followed by the remaining nine less signifi- cant bits. 12.4.2 ispi control register the ispi control register (spcr), along with the ispi interval control register, controls the operation of the ispi. follow this sequence when changing operating modes: 1. disable the ispi (count=0) without affecting other fields. 2. wait for any transfer to complete (xch bit clear). 3. update to the new mode. 4. re-enable the ispi (count = newcount). figure 12-4 ispi control register spdr ispi data register 10008000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rx data w tx data reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0+ spcr ispi control register 10008002 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r doze spi_en sns drv mstr irq_en pha pol spigp baud rate clock count w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola interval mode serial peripheral interface MMC2001 12-6 reference manual doze doze mode when the cpu executes a doze instruction and the system is placed in the doze mode, the doze bit affects operation of the ispi. when this bit is set, the ispi is dis- abled in doze mode. refer to the description in 12.6 ispi operation in low-power system modes . 0 = ispi unaffected in doze mode 1 = ispi disabled in doze mode at reset, this bit is cleared to zero. spi_en ispi enable in either master mode, this bit controls the value of the spi_en pin. the sense of the spi_en pin is determined by the sns bit. in interval mode, the spi_en pin is asserted only when xch is active. the spi_en bit must be programmed to a one for any master mode transfer to occur. in slave mode, the ispi state machine uses the input value on the spi_en pin, and this register bit is ignored. further, the spi_en register bit will not reflect the value of the spi_en pin in slave mode. 0 = negated 1 = asserted sns spi_en sense the sns bit controls the sense of the spi_en pin relative to the spi_en register bit in the ispi control register. this is required because in interval mode, the state machine must assert and then negate the spi_en pin. the sns bit has an effect only when the spi_en pin is an output. if the spi_en pin is an input, then it is active low, and the sns bit has no effect. 0 = spi_en pin is active low 1 = spi_en pin is active high drv drive type this bit controls the configuration of the spi_clk, spi_en and spi_mosi output buffers in either master mode of the ispi (mstr=1). in slave mode, this bit is ignored. 0 = outputs are totem-pole in either master mode 1 = outputs are open-drain in either master mode mstr master mode this bit controls the mode of the ispi. in slave mode, the spi_clk and spi_en pins are inputs; in the master modes, they are outputs. 0 = ispi operates in slave mode 1 = ispi operates in either interval mode or manual mode (see ivl_en in sicr) irq_en interrupt request enable this bit enables/disables the ispi interrupt request output signal. this bit is cleared to zero on reset. 0 = interrupts disabled 1 = interrupts enabled
MMC2001 interval mode serial peripheral interface motorola reference manual 12-7 pha phase this bit controls the phase shift of the spi_clk. (see figure 12-2 ) 0 = normal phase 1 = shift advance to opposite phase pol polarity this bit controls the polarity of the spi_clk. (see figure 12-2 ) 0 = normal polarity 1 = inverted polarity spigp spi_gp control this bit controls the data on the spi_gp pin. 0 = pin driven low 1 = pin driven high baud rate these bits select the baud rate of the ispi bit clock based on divisions of the system clock. the master clock for the ispi is hi_refclk. clock count these bits select the length of the transfer and control the justification of data. from two to 16 bits can be transferred. a count of all zeros causes the ispi to be disabled. 7deoh%$8'5$7()lhog6hwwlqjv value divide by 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024 7deoh&/2&.&2817)lhog6hwwlqjv value meaning 0000 disable ispi 0001 2-bit transfer . . . . 0111 8-bit transfer . . . . 1111 16-bit transfer
motorola interval mode serial peripheral interface MMC2001 12-8 reference manual 12.4.3 ispi interval control register the ispi interval control register (spicr) controls interval mode operation. figure 12-5 ispi interval control register lpbk loopback this bit enables a loopback test feature in the ispi. when looping back, the ispi operates as if the spi_miso and spi_mosi pins are wired together and there are no other external devices connected to the ispi data input pin. whenever loopback is enabled, the data read from the ispi data register after a given transfer matches what was written to the ispi data register prior to that transfer, masked if necessary to account for the number of bits transferred. 0 = loopback disabled 1 = loopback enabled ivl_en interval mode enable setting this bit places the ispi in interval mode. if the mstr bit in the ispi control register is cleared, then the ispi is operating in slave mode, and this bit is ignored. 0 = ispi is not operating in interval mode 1 = ispi is operating in interval mode if mstr=1 interval count in interval mode, this register value is loaded into the ispi interval timer upon comple- tion of a transfer. each bit-clock period, the value in this counter is decremented by one. when the value in the register reaches zero, then xch is set, and a new transfer is begun. 12.4.4 ispi status register the ispi status register (spsr) contains flags indicating whether an overrun condi- tion has occurred, whether an interrupt has been requested, and whether a transfer is being performed. figure 12-6 ispi status register spicr ispi interval control register 10008004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 lpbk ivl_en interval count w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spsr ispi status register 10008006 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ovr irq xch 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MMC2001 interval mode serial peripheral interface motorola reference manual 12-9 ovr overrun this bit is set by the ispi controller when a new value is loaded into the rx data reg- ister due to an overrun event. an overrun occurs whenever the rx data register is updated while holding previously received data that has not been read. this could occur when pin spi_en becomes inactive and the bit timer has already timed out, or when the bit counter times out a second time while spi_en remains continuously asserted. it could also be set in interval or manual master mode if the rx data regis- ter is not read between transfers. in these cases, the ovr bit may be ignored if appropriate. 0 = no overrun event has occurred 1 = an overrun event has occurred this bit is cleared by writing it to zero or by reset. irq interrupt request this register bit is cleared on either a write or a read of the ispi data register, and when set indicates that an interrupt has been requested. 0 = no interrupt has been requested 1 = an interrupt has been requested xch exchange this bit indicates whether the state machine is performing a transfer. in manual mode, xch is set by writing the ispi data register. in interval mode, xch is set auto- matically by the interval timer. in slave mode, xch is set when pin spi_en is asserted and is negated briefly once the counters determine the completion of a transfer. it is then reasserted if spi_en is still asserted. in all modes, xch is reset upon completion of a transfer. 0 = spi is idle or interval timer is operating 1 = initiate exchange or exchange in progress 12.5 ispi programming examples 12.5.1 manual mode example manual mode is the simplest of the transfer methods. assume that the transfer to be performed is bidirectional, and the receive data is 12 bits. the data to be sent is 0x0013, and the external device will receive and keep all 12 bits. the external device is such that pha=1, pol=0 is desired, with an active low enable. an interrupt is required following the transfer to indicate when data is avail- able. the device accepts data at a clock rate between 100 khz and 1 mhz, and the MMC2001 uses a 16.38-mhz clock. to program the ispi to perform such a transfer: 1. write ispi register spcr to 0x4e4b. 2. write ispi register spdr to 0x0013.
motorola interval mode serial peripheral interface MMC2001 12-10 reference manual the value to be written into the ispi control register is determined as follows: ? (assume doze = 0) ? assign sns = 0 to force enable to active low. ? assign spi_en = 1 to enable the pin ? assign mstr = 1 ? assign irq_en = 1 to enable interrupts ? assign pha = 1 ? assign pol = 0 ? assign baud rate = 4 to divide 16 mhz down to approximately 128 khz per bit ? assign clock count = 0xb to transfer 12 bits. 12.5.2 slave mode example in slave mode, the timing of transfers is dependent entirely on the external device. if the transfer parameters for this example are identical to those in the manual mode example above, then the ispi is programmed in a two-step process: 1. write ispi register spcr to 0x060b. 2. write ispi register spdr to 0x0013. spcr is programmed differently from the manual mode example because: ? spi_en, sns, and baud rate are ignored in slave mode. ? mstr has to be cleared to enable slave mode. 12.5.3 interval model example with a 16.38-mhz clock, hi_refclk = 61 ns. to program the ispi to transfer 10-bit words at 8-khz intervals: 1. program clock count to 0x9 2. program baud rate to 0x3 (divide hi_refclk by 64) 3. set spi_en, pha, pol, and sns as desired 4. program interval count to 0x29f (671 decimal) per the equation: time_of_interval = (hi_refclk_period * 2 * (interval_count+2)) + (hi_refclk_period * baud_count * (clock_count +1)) time_of_interval is then set to the following: 61 * 2 * (671 + 2) + (61 * 64 * 11) = 125.05 m s. the ispi interval timer begins as soon as written, following the transfer period. this leaves approximately 1406 hi_refclk cycles before the tx data register must be re-written.
MMC2001 interval mode serial peripheral interface motorola reference manual 12-11 12.6 ispi operation in low-power system modes the following table summarizes ispi operation in the different low-power modes. in most modes, the ispi operates as long as a clock is available. in doze mode, the ispi may be selectively disabled, depending on the value of the doze bit. in stop mode, the ispi halts immediately (due to halting of system clocks) and forgets the state of any transfer in operation (the state machine is reset, and the shift register is cleared). this is done to prevent hanging a transfer in the middle; it is assumed that when stop is initiated, there is some other method of shutting down external devices. the spdr value is retained so that the transfer can be re-initiated after the system is restarted by simply writing the spi control register. 12.7 ispi operation in system debug mode in debug mode, the only modification to ispi behavior is that the clear-on-access function of the irq bit in the spi status register is disabled. normally the irq bit is cleared on a read or write access to the spdr. table 12-4 ispi low-power mode operation state operation normal runs whenever enabled wait runs whenever enabled doze if doze is set (in spcr), then disabled stop disabled
motorola interval mode serial peripheral interface MMC2001 12-12 reference manual
MMC2001 external interrupts/gpio (edge port) motorola reference manual 13-1 section 13 external interrupts/gpio (edge port) 13.1 overview the MMC2001 has eight external interrupt pins. each pin can be configured individu- ally as a level-sensitive interrupt, an edge-detecting interrupt (rising edge, falling edge, or both), or a general-purpose i/o pin. figure 13-1 external interrupt/gpio block diagram 13.2 interrupt/general-purpose i/o pin descriptions (int[0:7]) when programmed as inputs, these pins use schmitt triggered input buffers. when edge triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increases, the probability of generating multiple interrupts due to this noise also increases. all default to general-purpose input pins at reset. the interrupt request function on these pins is masked in the interrupt controller fast interrupt enable register (fier) and nor- mal interrupt enable register (nier). eppar[2n] eppar[2n+1] eppar[2n+1] eppar[2n] to interrupt controller epddr[n] epdr[n] data rising edge detect falling edge detect epfr[n] bus eppar [2n, 2n+1]
motorola external interrupts/gpio (edge port) MMC2001 13-2 reference manual 13.3 edge port programming model the edge port programming model consists of the following registers: ? the edge port pin assignment register (eppar) controls the function of each pin individually. ? the edge port data direction register (epddr) controls the direction of each one of the pins individually. ? the edge port data register (epdr) holds the data to be driven to the pins. ? the edge port flag register (epfr) latches the edge event for each one of the pins individually. access the edge port registers with halfword accesses. 13.3.1 edge port pin assignment register (eppar) the 16-bit read/write edge port pin assignment register (eppar) configures each of the interrupt pins as either level-sensitive or edge-triggered. rising, falling, or both edges can be selected as the active edge. requests are always generated out of this block but may be masked within the interrupt controller module. the functionality of this register is independent of the programmed pin direction. figure 13-2 edge port pin assignment register eppax edge port pin assignment select field x pins configured as level-sensitive are inverted so that a logic low on the external pin represents a valid interrupt request. level-sensitive interrupt inputs are not latched. to guarantee that a level-sensitive interrupt request is acknowledged, the interrupt source must keep the signal asserted until acknowledged by software. pins configured as edge-sensitive interrupts are latched and need not remain asserted for interrupt generation. when the pin is programmed to use the edge detecting circuit, its state is monitored regardless of its configuration as input or out- put. table 13-1 gpio edge port address map address use access 10007000 edge port pin assignment register (eppar) supervisor only 10007002 edge port data direction register (epddr) supervisor only 10007004 edge port data register (epdr) supervisor only 10007006 edge port flag register (epfr) supervisor only eppar edge port pin assignment register 10007000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r eppa7 eppa6 eppa5 eppa4 eppa3 eppa2 eppa1 eppa0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MMC2001 external interrupts/gpio (edge port) motorola reference manual 13-3 these bits are cleared by hardware reset. 13.3.2 edge port data direction register (epddr) the 16-bit read/write edge port data direction register (epddr) controls the direction of the port pins. setting any bit in this register configures the corresponding pin as an output. clearing any bit in this register configures the corresponding pin as an input. pin direction is independent of the level/edge mode programmed. figure 13-3 edge port data direction register epddx edge port data direction x 0 = pin int x is an input. 1 = pin intx is an output. these bits are cleared by reset. 13.3.3 edge port data register (epdr) the edge port data register (epdr) is a 16-bit register. writes to epdr are stored in an internal latch, and if any pin of the port is configured as an output, the data stored for that bit is driven onto the pin. reads of this register return the value sensed on the pins for those pins configured as inputs, or the data stored in the register for the pins configured as outputs. x = unaffected by reset figure 13-4 edge port data register table 13-2 eppax field settings value meaning 00 pin intx defined as level sensitive 01 pin intx defined as rising edge detect 10 pin intx defined as falling edge detect 11 pin intx defined as both falling and rising edge detect epddr edge port data direction register 10007002 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 epdd7 epdd6 epdd5 epdd4 epdd3 epdd2 epdd1 epdd0 w reset: 0 0 0 0 0 0 0 0 epdr edge port data register 10007004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 epd7 epd6 epd5 epd4 epd3 epd2 epd1 epd0 w reset: x x x x x x x x
motorola external interrupts/gpio (edge port) MMC2001 13-4 reference manual epdx edge port data x see the description above. these bits are not affected by hardware reset. 13.3.4 edge port flag register (epfr) the 16-bit read/write edge port flag register (epfr) indicates whether the selected edge has been detected on the port pins. figure 13-5 edge port flag register epfx edge port flag x 0 = selected edge for intx pin has not been detected. 1 = selected edge for intx pin has been detected. bits in this register are set when the programmed edge is detected on the corre- sponding pin. a bit remains set until cleared by writing it to a one. pin transitions do not affect this register if the pin is configured as level sensitive (epparx=00). the corresponding flag bit(s) are cleared to zero in this case. when a pin is configured as a general-purpose output, writes to epdr that cause the selected level or edge inter- rupt will set the corresponding bit in epfr. the outputs of this register drive the cor- responding input of the interrupt controller for those bits configured as edge detecting. these bits are cleared by hardware reset. epfr edge port flag register 10007006 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 epf7 epf6 epf5 epf4 epf3 epf2 epf1 epf0 w reset: 0 0 0 0 0 0 0 0
MMC2001 keypad port motorola reference manual 14-1 section 14 keypad port 14.1 overview the keypad port (kpp) is a 16-bit peripheral which can be used either for keypad matrix scanning or as general-purpose i/o. the block diagram of the kpp is shown in figure 14-1 . figure 14-1 kpp block diagram kpdr[15:8] kddr[15:8] kpdr[7:0] keypad matrix up to 8 x 8 kpcr[15:8] kddr[7:0] debounce chain kpsr to interrupt controller kpcr[7:0] 256 hz pad drivers row enable data direction (kddr) and open drain enable (kpcr) controls pull-up/data direction controls (kddr) controls (kpcr)
motorola keypad port MMC2001 14-2 reference manual 14.2 kpp pin description sixteen pins are dedicated to the kpp. keypads of any configuration up to eight rows and eight columns are supported through software configuration of the peripheral pins. any pins not used for the keypad are available for general-purpose input/output. the registers are configured such that the pins can be treated as an i/o port up to 16 bits wide. 14.2.1 input pins any of the 16 pins associated with the kpp can be configured as inputs by writing zeros to the appropriate bits in the kddr. additionally, the least significant eight bits (row inputs) corresponding to kddr[7:0] have internal pull-ups that are enabled when the pin is used as an input. 14.2.2 output pins any of the 16 pins associated with the kpp can be configured as outputs by writing the appropriate bits in the kddr to one. additionally, the pins representing the eight most significant bits (kddr[15:8]) can be designated as open drain outputs by writing a one into the appropriate bits in kpcr. the pins representing the lower eight bits (kddr[7:0]) are always totem-pole style drive when configured as outputs. 14.3 kpp programming model 14.3.1 keypad control register (kpcr) the keypad control register (kpcr) determines which of the eight possible column strobes are to be open drain when configured as outputs and which of the eight row sense lines are considered in generating an interrupt to the cpu. table 14-1 keypad port column modes kddr[15:8] kpcr[15:8] pin function 0 x input 1 0 totem-pole output 1 1 open-drain output table 14-2 keypad port address map address use access 10003000 keypad control register (kpcr) supervisor only 10003002 keypad status register (kpsr) supervisor only 10003004 keypad data direction register (kddr) supervisor only 10003006 keypad data register (kpdr) supervisor only 10003008 to 10003fff reserved supervisor only
MMC2001 keypad port motorola reference manual 14-3 setting a column open-drain enable bit (kco[7:0]) disables the pull-up driver on that pin. clearing the bit allows the pin to drive to the high state. this bit has no effect when the pin is configured as an input. setting a row enable control bit in this register enables the corresponding row line to participate in interrupt generation. likewise, clearing a bit disables that row from being used to generate an interrupt. this register is cleared by reset, disabling all rows. the row enable logic is independent of the programmed direction of the pin. writing a zero to the data register of pins configured as outputs causes a keypad interrupt to be generated if the row enable associated with that bit is set. it is up to the programmer to ensure that pins being used for functions other than the keypad are properly disabled. the kpcr register is byte or halfword addressable. figure 14-2 keypad control register kcox keypad column strobe open-drain enable x 0 = column strobe output x is totem-pole drive (p-channel enabled). 1 = column strobe output x is open drain (p-channel disabled). krex keypad row enable x 0 = row x is not included in keypad key press detect. 1 = row x is included in keypad key press detect. 14.3.2 keypad status register (kpsr) the keypad status register (kpsr) reflects the state of the keypress detect circuit. the keypad key depress (kpkd) status bit is set when one or more enabled rows are detected low after synchronization. the kpkd status bit remains set until cleared by software. the kpkd bit may be used to generate a maskable key depress interrupt. if desired, software may clear the keypress synchronizer chain to allow a repeated interrupt to be generated while a key remains pressed. in this case, a new interrupt will be generated after the synchronizer delay elapses if a key remains pressed. the keypad key release (kpkr) status bit is set when all enabled rows are detected high after synchronization. the kpkr status bit remains set until cleared by software. the bit will typically not be set again until the detect circuit senses a key depressed followed by all keys released. the kpkr bit may be used to generate a maskable key release interrupt. the key release synchronizer may be set high by software after scanning the keypad to ensure a known state. kpcr keypad control register 10003000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r kco7 kco6 kco5 kco4 kco3 kco2 kco1 kco0 kre7 kre6 kre5 kre4 kre3 kre2 kre1 kre0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola keypad port MMC2001 14-4 reference manual due to the logic function of the release and depress synchronizer chains, it is possi- ble to see the re-assertion of a status flag (kpkd or kpkr) if it is cleared by software prior to the system exiting the state it represents. software should ensure that the interrupt for a key release event is masked until it has entered the key pressed state (and vice versa) unless this activity is desired, as might be the case when a repeated interrupt is to be generated. the synchronizer chains are capable of being initialized to detect repeated key presses or releases. if they are not initialized when the corre- sponding event flag is cleared, false interrupts may be generated for depress (or release) events shorter than the length of the corresponding chain. the kpsr register is byte or halfword addressable. figure 14-3 keypad status register krie key release interrupt enable 0 = no interrupt request is generated when kpkr is set 1 = an interrupt request is generated when kpkr is set kdie key depress interrupt enable 0 = no interrupt request is generated when kpkd is set 1 = an interrupt request is generated when kpkd is set krss key release synchronizer set the key release synchronizer is set by writing a logic one into this bit. reads return a value of zero. kdsc key depress synchronizer clear the key depress synchronizer is cleared by writing a logic one into this bit. reads return a value of zero. kpkr keypad key release 0 = no key release detected 1 = all keys have been released kpkr is cleared by writing a logic one into this bit. kpkd keypad key depress 0 = no key presses detected 1 = a key has been depressed kpkd is cleared by writing a logic one into this bit. kpsr keypad status register 10003002 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 krie kdie 0 0 0 0 0 0 kpkr kpkd w krss kdsc reset: 0 0 0 0 0 0
MMC2001 keypad port motorola reference manual 14-5 14.3.3 keypad data direction register (kddr) the bits in the keypad data direction register (kddr) control the direction of the key- pad port pins. the upper eight bits in the register affect the pins designated as col- umn strobes, while the lower eight bits affect the row sense pins. setting any bit in this register configures the corresponding pin as an output. clearing any bit in this register configures the corresponding port pin as an input. for bits 7 to 0, an internal pull-up is enabled if the corresponding bit is cleared. this register is cleared by reset, configuring all pins as inputs. the kddr register is byte or halfword addressable. figure 14-4 keypad data direction register kcddx keypad column x data direction 0 = colx pin is configured as input. 1 = colx pin is configured as output. krddx keypad row x data direction 0 = rowx pin is configured as input. 1 = rowx pin is configured as output. 14.3.4 keypad data register (kpdr) the 16-bit keypad data register is used to access the column and row data. data writ- ten to this register is stored in an internal latch, and for each pin configured as an out- put, the stored data is driven onto the pin. a read of this register returns the value on the pin for those bits configured as inputs. otherwise, the value read is the value stored in the register. the kpdr register is byte or halfword addressable. * since pins default to inputs, reset value is determined by the logic level present on the pins at reset. figure 14-5 keypad data register kddr keypad data direction register 10003004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r kcdd7 kcdd6 kcdd5 kcdd4 kcdd3 kcdd2 kcdd1 kcdd0 krdd7 krdd6 krdd5 krdd4 krdd3 krdd2 krdd1 krdd0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 kpdr keypad data register 10003006 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r kcd7 kcd6 kcd5 kcd4 kcd3 kcd2 kcd1 kcd0 krd7 krd6 krd5 krd4 krd3 krd2 krd1 krd0 w reset: * * * * * * * * * * * * * * * *
motorola keypad port MMC2001 14-6 reference manual kcdx keypad column x data bit krdx keypad row x data bit this register is not initialized by reset. valid data should be written to this register before any bits are configured as outputs. 14.4 keypad operation the keypad port is designed to simplify the software task of scanning a keypad matrix. with appropriate software support, the kpp is capable of detecting, debounc- ing, and decoding one or two keys pressed simultaneously in the keypad. logic in the kpp can detect a key press even while the processor is in one of the low- power standby modes. the kpp may generate a cpu interrupt any time a key press or key release is detected. this interrupt can force the processor out of a low-power mode. 14.4.1 keypad matrix construction the keypad port is designed to interface to a keypad matrix which shorts the inter- secting row and column lines together whenever a key is depressed. the interface is not optimized for other switch configurations. 14.4.2 keypad port configuration software must initialize the keypad port for the size of the keypad matrix. pins con- nected to the keypad columns should be configured as open-drain outputs. pins con- nected to the keypad rows should be configured as inputs. on-chip pull-up resistors are implemented for active keypad rows, as defined in section 4 signal descriptions . row inputs must also be enabled in the keypad control register to be active in the interrupt generation circuit. discrete switches that are not part of the matrix may be connected to any unused row inputs. the second terminal of the discrete switch is connected to ground. the hard- ware detects closures of these switches without the need for software polling. 14.4.3 keypad matrix scanning keypad scanning is performed by a software loop that walks a zero across each of the keypad columns, reading the value on the rows at each step. the process is repeated several times in succession, with the results of each pass optionally com- pared with those from the previous pass. when three or four consecutive scans yield the same key closures, a valid key press has been detected. software can then decode exactly which switch was depressed and pass the value up to the next higher software layer. the basic debouncing period to be defined in the software routine can be controlled with an internal timer. the basic period is the period between the scan of two consec- utive columns, so the debounce time between two consecutive scans of the whole matrix equals the number of columns multiplied by the basic period.
MMC2001 keypad port motorola reference manual 14-7 14.4.4 keypad standby there is no need for the cpu to scan the keypad continually. between key presses, the keypad can be left in a state that requires no software intervention until the next key press is detected. to place the keypad in a standby state, software writes all col- umn outputs low. row inputs are left enabled. at this point the cpu can attend to other tasks or revert to a low-power standby mode. the keypad port will interrupt the cpu if any key is pressed. upon receiving a keypad interrupt, the cpu should set all the column strobes high and begin a normal keypad scanning routine to determine which key was pressed. it is important that open-drain drivers be used when scanning to prevent a possible dc path between power and ground through two or more switches. 14.4.5 glitch suppression on keypad inputs a glitch suppression circuit qualifies the keypad inputs to prevent noise from inadvert- ently interrupting the cpu. the circuit is a four-state synchronizer clocked from a 256-hz clock source. this clock must continue to run in any low-power mode for which the keypad is a wake-up source, as the cpu interrupt is generated from the synchronized input. an interrupt is not generated until all four synchronizer stages have latched a valid key assertion, effectively filtering out any noise less than 16 ms in duration. the interrupt output is latched in an s-r latch and remains asserted until cleared by software. the set input of the latch is clocked on the rising edge.
motorola keypad port MMC2001 14-8 reference manual figure 14-6 keypad synchronizer functional diagram 14.4.6 multiple key closures one or two keys pressed simultaneously are easily detected by the software. when three or more keys are pressed, however, it is possible that errant key closures may be detected. as can be seen in figure 14-7 , three keys pressed simultaneously can short between the column currently scanned by software and another column. depending on the location of the third key pressed, a ghost key press may be detected. keypad 256 hz matrix . . . ff dq ff dq ff dq ff dq ^s r clear kpkd status flag nand r r r r kpkd ff dq ff dq ff dq ff dq ^s r s s s s kpkr clear kpkr status flag clear kpkd synchronizer set kpkr synchronizer
MMC2001 keypad port motorola reference manual 14-9 figure 14-7 decoding wrong three key presses 14.4.7 typical keypad configuration and scanning sequence 1. configure keypad a. enable number of rows in keypad (kpcr[7:0]). b. write zeros to kpdr[15:8]. c. configure keypad columns as open-drain (kpcr[15:8]). d. configure columns as output, rows as input (kddr[15:0]). e. clear the kpkd status flag and synchronizer chain. f. set the kdie control bit, and clear the krie control bit (avoid false release events). (now in standby mode, awaiting a keypress...) 2. keypress interrupt detected 3. begin keypad scanning routine a. disable keypad interrupts. b. write ones to kpdr[15:8], setting column data to ones. c. configure columns as totem-pole outputs. d. configure columns as open-drain. e. write a single column to zero, and write others to one. f. sample row inputs and save data. multiple key presses can be detected on a single column. g. repeat steps b to f for remaining columns. h. return all columns to zero in preparation for standby mode. column pulled down column not pulled down pulled down row pulled down row three real key presses ghost key press the path of the zero pull down that reaches the wrong row and so generates a ghost key press
motorola keypad port MMC2001 14-10 reference manual i. clear interrupt status bit(s) by writing to a one; set the kpkr synchronizer chain, clear the kpkd synchronizer chain. j. re-enable the appropriate keypad interrupt(s); kdie to detect a key hold condition, or krie to detect a key release event.
MMC2001 pulse width modulator motorola reference manual 15-1 section 15 pulse width modulator the pulse width modulator (pwm) module contains six identical channels, pwm5 C pwm0. 15.1 overview each pwm channel consists of a simple free-running counter with two compare reg- isters. each compare register performs a particular task when it matches the count value. the period comparator causes the output pin to be set and the free-running counter to reset when its value matches the period value. the width comparator causes the output pin to reset when the counter value matches. with a suitable low- pass filter, the pwm channel can be used as a digital-to-analog converter. figure 15-1 is a block diagram of a single pwm channel. figure 15-1 pwm block diagram by feeding a stream of sample values to the pwm into the width register and provid- ing a low-pass filter on the output, the output pin can provide a digitally-generated sound source. the reconstruction rate is determined by the selected period. typically, for voice quality, the rate is between 6 khz and 8 khz. figure 15-2 relates the pulse stream to the filtered audio output. figure 15-2 pwm generating audio system clock clockgen (prescaler) width compare counter period compare output control pulse output pulse stream filtered audio
motorola pulse width modulator MMC2001 15-2 reference manual the width and period registers are double-buffered so that a new value can be loaded for the next cycle without disturbing the current cycle. at the beginning of each period, the contents of the buffer registers are loaded into the comparator for the next cycle. sampled audio can be recreated by feeding a new sample value into the width regis- ter on each interrupt. a single shared prescaler provides operating flexibility. figure 15-3 describes its functionality. the prescaler contains a variable divider that can divide the incoming clock by certain values between four and 65536. figure 15-3 pwm prescaler each pwm channel can independently select a prescaler tap point. in addition, each channel provides a maskable interrupt request that can be asserted after each period compare event. channels can be used as periodic interrupt sources. in this case, the output pin asso- ciated with a channel can be used as a general-purpose i/o pin operating indepen- dently of the timing function. 15.2 pwm programming model this section describes the registers and control bits in the pwm module. all registers reset to 0x0000 after reset. these registers must be accessed with halfword accesses. accesses other than half- word in size result in undefined activity. divide by 4 divide by 2 divide by 2 divide by 4 divide by 4 divide by 8 divide by 8 divide by 4 pclk clk clk sel sel hi_refclk
MMC2001 pulse width modulator motorola reference manual 15-3 table 15-1 pwm address map address use access 10005000 pwm0 control register (pwmcr0) supervisor only 10005002 pwm0 period register (pwmpr0) supervisor only 10005004 pwm0 width register (pwmwr0) supervisor only 10005006 pwm0 counter register (pwmctr0) supervisor only 10005008 pwm1 control register (pwmcr1) supervisor only 1000500a pwm1 period register (pwmpr1) supervisor only 1000500c pwm1 width register (pwmwr1) supervisor only 1000500e pwm1 counter register (pwmctr1) supervisor only 10005010 pwm2 control register (pwmcr2) supervisor only 10005012 pwm2 period register (pwmpr2) supervisor only 10005014 pwm2 width register (pwmwr2) supervisor only 10005016 pwm2 counter register (pwmctr2) supervisor only 10005018 pwm3 control register (pwmcr3) supervisor only 1000501a pwm3 period register (pwmpr3) supervisor only 1000501c pwm3 width register (pwmwr3) supervisor only 1000501e pwm3 counter register (pwmctr3) supervisor only 10005020 pwm4 control register (pwmcr4) supervisor only 10005022 pwm4 period register (pwmpr4) supervisor only 10005024 pwm4 width register (pwmwr4) supervisor only 10005026 pwm4 counter register (pwmctr4) supervisor only 10005028 pwm5 control register (pwmcr5) supervisor only 1000502a pwm5 period register (pwmpr5) supervisor only 1000502c pwm5 width register (pwmwr5) supervisor only 1000502e pwm5 counter register (pwmctr5) supervisor only 10005030 to 10005fff reserved supervisor only 10006000 to 10006fff not used (access causes transfer error) not applicable
motorola pulse width modulator MMC2001 15-4 reference manual 15.2.1 pwm control register the pwm control register (pwmcr) controls the overall operation of the pwm chan- nel. the status of the channel pin is also accessible. figure 15-4 pwm control registers doze doze mode when the cpu executes a doze instruction and the system is placed in doze mode, the doze bit affects operation of the pwm channel. if this bit is set, the pwm chan- nel is disabled in doze mode. pwm channel operation is suspended at the end of the current period. if irq_en is set, an interrupt request is still generated following the period compare that causes suspension. this interrupt can selectively cause the cpu to exit doze mode. 0 = pwm channel is unaffected in doze mode 1 = pwm channel is disabled in doze mode at reset, this bit is cleared to zero. pwm irq pwm interrupt request this bit indicates that an interrupt was posted by a period compare. this bit can be set by the user to post a pwm interrupt immediately for debugging purposes. this bit is cleared automatically after it is read while set. if irq en is cleared, this bit will not be set. 0 = no interrupt posted 1 = pwm period rolled over irq en interrupt request enable this bit controls pwm interrupt generation. while this bit is low, the interrupt is dis- abled. 0 = pwm interrupt disabled 1 = pwm interrupt enabled load load pwmpr and pwmwr setting this bit forces a new period. the period and width registers are loaded into the comparator latches and the counter is reset. this bit is cleared automatically after the load has been performed. the actual load occurs some time after the cpu writes this pwmcr0 pwm0 control register 10005000 pwmcr1 pwm1 control register 10005008 pwmcr2 pwm2 control register 10005010 pwmcr3 pwm3 control register 10005018 pwmcr4 pwm4 control register 10005020 pwmcr5 pwm5 control register 10005028 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 doze pwm irq irq en load data dir pol mode count en clksel w reset: 0 0 0 0 0 0 0 0 0 0 0
MMC2001 pulse width modulator motorola reference manual 15-5 bit, as the load occurs on the next rising pclk edge following internal synchroniza- tion. forcing a load of the comparator latches and counter in this manner must be done with caution to avoid unexpected pin behavior. data pwm data this bit indicates or controls the current state of the pwm pin. when the pin is config- ured as a general-purpose output, the logical value written to this bit is used to drive the pin. when the pin is configured as a general-purpose input, the pin value is reflected by this bit. when the pin is configured in pwm mode, the bit reflects the value being driven on the pin by the pwm logic. dir direction this bit controls the direction of the pin when used as a gpio pin. this bit has no effect when mode indicates pwm mode. 0 = pin is an input pin 1 = pin is an output pin pol polarity this bit controls the polarity of the pin when used as a pwm output pin. normally, the output pin is set high at period boundaries and goes low when a width compare event occurs. this bit is ignored if the pin is being used as a gpio pin. 0 = normal pwm polarity 1 = inverted pwm polarity mode pwm mode this bit selects whether the pwm pin is used for gpio or for the pwm function. 0 = general-purpose i/o mode 1 = pwm mode count en counter enable this bit enables or disables the pwm counter. the counter is actually enabled or dis- abled some time after the cpu writes this bit. it is enabled on the next rising pclk edge following internal synchronization. if running, the counter is disabled following the next period match. 0 = pwm disabled. while disabled, the counter is in a low-power mode and does not count. the following events occur: when the output pin is configured to operate in pwm mode (mode = 1), the output pin is forced to the setting of the pol bit. the counter is reset to 00 and frozen. the contents of the width and period registers are loaded into the compara- tors. the comparators are disabled. if the counter has been running, and the actual disable occurs at the occur- rence of a period match, an interrupt request may still be generated, even though the counter is being disabled. to prevent this, write the interrupt enable control bit (irq_en) to zero when disabling the counter.
motorola pulse width modulator MMC2001 15-6 reference manual 1 = pwm is enabled and begins a new period. the following events occur: the output pin changes state to start a new period (if width != 0 and period != 0 and width < period) the counter is released and begins counting the comparators are enabled the pwm irq bit is set, indicating the start of a new period if irq en is set. clk sel clock select these bits select the output of the divider chain. 15.2.2 pwm period register the pwm period register (pwmpr) controls the period of the pwm by defining the number of pclks in the period. when the counter value matches the value in this register, an interrupt is posted and the counter is reset to start another period. figure 15-5 pwm period registers period pulse period this is the value that causes the counter to be reset. there is one special case. when period = 0, the output is never set high (0% duty cycle). in this case, the compara- tor is loaded and the counter reset on every pclk. in addition, if enabled, an interrupt request is generated on every pclk. 7deoh&/.6(/)lhog6hwwlqjv value divide by 000 4 001 8 010 16 011 64 100 256 101 2048 110 16384 111 65536 pwmpr0 pwm0 period register 10005002 pwmpr1 pwm1 period register 1000500a pwmpr2 pwm2 period register 10005012 pwmpr3 pwm3 period register 1000501a pwmpr4 pwm4 period register 10005022 pwmpr5 pwm5 period register 1000502a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 period w reset: 0 0 0 0 0 0 0 0 0 0
MMC2001 pulse width modulator motorola reference manual 15-7 15.2.3 pwm width register the pwm width register (pwmwr) defines the width of the pulse in pclks. when the counter matches the value in this register, the output is reset for the duration of the period. note that if the value in this register is not less than the period register, the output will never be reset, resulting in a 100% duty cycle. figure 15-6 pwm width registers width pulse width when the counter reaches the value in this register, the output is reset. 15.2.4 pwm counter register the read-only pwm counter register (pwmctr) holds the current count value. it can be read at any time without disturbing the counter. figure 15-7 pwm count registers count count value this is the current count value. pwmwr0 pwm0 width register 10005004 pwmwr1 pwm1 width register 1000500c pwmwr2 pwm2 width register 10005014 pwmwr3 pwm3 width register 1000501c pwmwr4 pwm4 width register 10005024 pwmwr5 pwm5 width register 1000502c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 width w reset: 0 0 0 0 0 0 0 0 0 0 pwmctr0 pwm0 counter register 10005006 pwmctr1 pwm1 counter register 1000500e pwmctr2 pwm2 counter register 10005016 pwmctr3 pwm3 counter register 1000501e pwmctr4 pwm4 counter register 10005026 pwmctr5 pwm5 counter register 1000502e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 count w reset: 0 0 0 0 0 0 0 0 0 0
motorola pulse width modulator MMC2001 15-8 reference manual 15.3 pwm operating range table 15-3 shows the operating range and resolution of the pwm with a 16-mhz hi_refclk. the minimum period range assumes a value of two in the period regis- ter, while the maximum assumes a value of 256. 15.4 pwm operation in low-power system modes table 15-4 summarizes pwm operation in the different low-power modes. in most modes, the pwm operates as long as a clock is available. in doze mode, the pwm channels may be selectively disabled, depending on the value of the doze control bit. pwm channel operation will be suspended at the end of the current period. in stop mode, the pwm halts immediately (due to halting of system clocks) and forgets the state of any period (the state machine is reset, and the shift register is cleared). it is assumed that when stop is initiated, the channels have been disabled. table 15-3 pwm range at 16 mhz divide by approximate period range at 16 mhz resolution at 16 mhz 40.5 m s C 256 m s.25 m s 81 m s C 512 m s.5 m s 16 2 m s C 1 ms 1 m s 64 8 m s C 4.1 ms 4 m s 256 32 m s C 16.5 ms 16 m s 2048 256 m s C 65.6 ms 128 m s 16384 2 ms C 1 s 1 ms 65536 8.2 ms C 4 s 4.1 ms table 15-4 pwm low-power mode operation mode operation normal runs whenever enabled wait runs whenever enabled doze if doze is set (in pwm control register), then disabled. stop disabled
MMC2001 once? debug module motorola reference manual 16-1 section 16 once? debug module 16.1 overview the on-chip emulation (once?) circuitry provides a simple, inexpensive debugging interface that allows external access to the processors internal registers and to mem- ory/peripherals. once capabilities are controlled through a serial interface, mapped onto a jtag test access port (tap) protocol. figure 16-1 shows the components of the once circuitry. figure 16-1 once block diagram the interface to the once controller and its resources is based on the tap defined for jtag in the ieee-1149.1a-1993 standard. 16.2 operation an instruction is scanned into the once module through the serial interface and then decoded. data may then be scanned in and used to update a register or resource on a write to the resource, or data associated with a resource may be scanned out for a read of the resource. pstat attr addr tdo tms tdi tck breakpoint and trace logic once controller and serial interface breakpoint registers and comparators pc fifo pipeline information trst brkrq dbgrq debug dbgack idr de
motorola once? debug module MMC2001 16-2 reference manual for accesses to the cpu internal state, the once controller requests the cpu to enter debug mode via the cpu dbgrq input. once cpu debug mode has been entered, as indicated by the once status register, the processor state may be accessed through the cpu scan register. the once controller is implemented as a 16-state fsm, with a one-to-one corre- spondence to the states defined for the jtag tap controller. cpu registers and the contents of memory locations are accessed by scanning instructions and data into and out of the cpu scan chain. required data is accessed by executing the scanned instructions. memory locations may be read by scanning in a load instruction to the cpu that references the desired memory location, executing the load instruction, and then scanning out the result of the load. other resources are accessed in a similar manner. figure 16-2 once controller capture - dr shift - dr exit1 - dr pause - dr exit2 - dr update - dr select - ir scan capture - ir shift - ir exit1 - ir pause - ir exit2 - ir update - ir select dr- scan run-test/idle test-logic-reset 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 0 0 00 0 0 0 0 0 0 0 0 0
MMC2001 once? debug module motorola reference manual 16-3 resources contained in the once module that do not require the cpu to be halted for access may be controlled while the cpu is executing and do not interfere with normal processor execution. accesses to certain resources, such as the pc fifo and the count registers, while not part of the cpu, may require the cpu to be stopped to allow access to avoid synchronization hazards. if it is known that the cpu clock is enabled and running no slower than the tck input, there is sufficient syn- chronization performed to allow reads but not writes of these specific resources. debug firmware may ensure that it is safe to access these resources by reading the osr to determine the state of the cpu prior to access. all other cases require the cpu to be in the debug state for deterministic operation. 16.3 once pins the following paragraphs describe the pins associated with the once controller and serial interface component. the once pin interface is used to transfer once instructions and data to the once control block. depending on the particular resource being accessed, the cpu may need to be placed in debug mode. for resources outside of the cpu block and con- tained in the once block, the processor is not disturbed and may continue execution. if a processor resource is required, the once controller may assert a debug request (dbgrq ) to the cpu. this causes the cpu to finish the instruction being executed, save the instruction pipeline information, enter debug mode, and wait for further com- mands. asserting dbgrq causes the device to exit stop, doze, or wait mode. 16.3.1 debug serial input (tdi) data and commands are provided to the once controller through the tdi pin. data is latched on the rising edge of the tck serial clock. data is shifted into the once serial port least significant bit (lsb) first. 16.3.2 debug serial clock (tck) the tck pin supplies the serial clock to the once control block. the serial clock pro- vides pulses required to shift data and commands into and out of the once serial port. (data is clocked into the once on the rising edge and is clocked out of the once serial port on the falling edge.) the debug serial clock frequency must be no greater than 50% of the processor clock frequency. 16.3.3 debug serial output (tdo) serial data is read from the once block through the tdo pin. data is always shifted out the once serial port lsb first. data is clocked out of the once serial port on the falling edge of tck. tdo is three-stateable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. 16.3.4 debug mode select (tms) the debug mode select input is used to cycle through states in the once debug con- troller. toggling the tms pin while clocking with tck controls the transitions through the tap state controller.
motorola once? debug module MMC2001 16-4 reference manual 16.3.5 test reset (trst ) the test reset input is used to reset the once controller externally by placing the once control logic in a test logic reset state. once operation is disabled in the reset controller and reserved states. 16.3.6 debug event (de ) the debug event (de ) pin is a bidirectional open drain pin. as an input, de provides a fast means of entering debug mode from an external command controller. as an out- put, this pin provides a fast means of acknowledging debug mode entry to an external command controller. the assertion of this pin by a command controller causes the cpu to finish the cur- rent instruction being executed, save the instruction pipeline information, enter debug mode, and wait for commands to be entered from the tdi line. if de was used to enter debug mode, then de must be negated after the once responds with an acknowledgment and before sending the first once command. the assertion of this pin by the cpu acknowledges that it has entered debug mode and is waiting for commands to be entered from the tdi line. 16.4 once controller and serial interface figure 16-3 is a block diagram of the once controller and serial interface. figure 16-3 once controller and serial interface once command register tdi tck status and control registers tdo mode select once decoder isbkpt isdr istrace register write register read tap tms cpu control/status controller
MMC2001 once? debug module motorola reference manual 16-5 the once controller and serial interface contain the following blocks: once tap controller, the once command register, once decoder, and the once control and status registers. the once command register acts as the ir for the tap controller. all other once resources are treated as data registers (dr) by the tap controller. the command register is loaded by serially shifting in commands during the tap controller shift-ir state, and is loaded during the update-ir state. the command register selects a once resource to be accessed as a data register (dr) during the tap controller cap- ture-dr, shift-dr and update-dr states. 16.5 once interface signals the following paragraphs describe the once interface signals to other internal blocks associated with the once controller. these signals are not available externally, and descriptions are provided to improve understanding of once operation. 16.5.1 internal debug request input (idr ) the internal debug request input is a hardware signal which is used in some imple- mentations to force an immediate debug request to the cpu. if present and enabled, it functions in an identical manner to the control function provided by the dr control bit in the once control register (ocr). this input is maskable by a control bit in ocr. 16.5.2 cpu debug request (dbgrq ) the dbgrq signal is asserted by the once control logic to request the cpu to enter the debug state. it may be asserted for a number of different conditions. assertion of this signal causes the cpu to finish the current instruction being executed, save the instruction pipeline information, enter debug mode, and wait for further commands. asserting dbgrq causes the device to exit stop, doze, or wait mode. 16.5.3 cpu debug acknowledge (dbgack ) the cpu asserts the dbgack signal upon entering the debug state. this signal is part of the handshake mechanism between the once control logic and the cpu. 16.5.4 cpu breakpoint request (brkrq ) the brkrq signal is asserted by the once control logic to signal that a breakpoint condition has occurred for the current cpu bus access. 16.5.5 cpu address, attributes (addr, attr) the cpu address and attribute information may be used in the memory breakpoint logic to qualify memory breakpoints with access address and cycle type information. 16.5.6 cpu status (pstat) the trace logic uses the cpu pstat signals to qualify trace count decrements with specific cpu activity.
motorola once? debug module MMC2001 16-6 reference manual 16.5.7 once debug output (debug ) the once debug output (debug ) is used to indicate to on-chip resources that a debug session is in progress. peripherals and other units may use this signal to mod- ify normal operation for the duration of a debug session. this may involve the cpu executing a sequence of instructions solely for the purpose of visibility/system con- trol. these instructions are not part of the normal instruction stream the cpu would have executed had it not been placed in debug mode. this signal is asserted the first time the cpu enters the debug state and remains asserted until the cpu is released by a write to the once command register with the go and ex bits set, and a register specified as either no register selected or the cpuscr. this signal remains asserted even though the cpu may enter and exit the debug state for each instruction executed under control of the once controller. see 16.6.1 once command register (ocmr) for more information on the function of the go and ex bits. 16.6 once controller registers this section describes the once controller registers: ? once command register (ocmr) ? once control register (ocr) ? once status register (osr) all once registers are addressed by means of the rs field in the omcr, as shown in table 16-1 . other once registers are described in 16.8 memory breakpoint logic and 16.9 once trace logic . 16.6.1 once command register (ocmr) the once command register (ocmr) is an 8-bit shift register that receives its serial data from the tdi pin. this register corresponds to the jtag ir, and is loaded when the update-ir tap controller state is entered. it holds the 8-bit commands shifted in during the shift-ir controller state to be used as input for the once decoder. the ocmr contains fields for controlling access to a once resource, as well as control- ling single-step operation, and exit from once mode. although the ocmr is updated during the update-ir tap controller state, the corre- sponding resource is accessed in the dr scan sequence of the tap controller, and as such, the update-dr state must be transitioned through in order for an access to occur. in addition, the update-dr state must also be transitioned through in order for the single-step and/or exit functionality to be performed, even though the command appears to have no data resource requirement associated with it. the command register is shown in figure 16-4 .
MMC2001 once? debug module motorola reference manual 16-7 figure 16-4 once command register r/w read/write command the r/w bit specifies the direction of data transfer. 0 = write the data associated with the command into the register specified by the rs field. 1 = read the data contained in the register specified by the rs field. go go command when the go bit is set, the device executes the instruction that resides in the ir reg- ister in the cpuscr. to execute the instruction, the processor leaves debug mode, executes the instruction, and if the ex bit is cleared, returns to debug mode immedi- ately after executing the instruction. the processor resumes normal operation if the ex bit is set. the go command is executed only if the operation is a read/write to either cpuscr or no register selected. otherwise, the go bit is ignored. the pro- cessor leaves debug mode after the tap controller update-dr state is entered. 0 = inactive (no action taken) 1 = execute instruction in ir ex exit command when the ex bit is set, the processor leaves debug mode and resumes normal oper- ation until another debug request is generated. the exit command is executed only if the go command is issued, and the operation is a read/write to cpuscr or read/ write to no register selected. otherwise the ex bit is ignored. the processor exits debug mode after the tap controller update-dr state is entered. 0 = remain in debug mode 1 = leave debug mode rs register select the register select bits define the source or destination register for the read or write operation, respectively. table 16-1 shows once register addresses. 2&052 2q&(&rppdqg5hjlvwhu %,7%,7 5: *2 (; 56
motorola once? debug module MMC2001 16-8 reference manual 16.6.2 once control register (ocr) the once control register (ocr) is a 32-bit register used to select the events that will put the device in debug mode and to enable or disable sections of the once logic. the control bits are read/write. figure 16-5 once control register table 16-1 once register addressing rs register selected 00000 reserved 00001 reserved 00010 reserved 00011 trace counter (otc) 00100 memory breakpoint counter a (mbca) 00101 memory breakpoint counter b (mbcb) 00110 program counter fifo and increment counter 00111 breakpoint address base register a (baba) 01000 breakpoint address base register b (babb) 01001 breakpoint address mask register a (bama) 01010 breakpoint address mask register b (bamb) 01011 cpu scan register (cpuscr) 01100 no register selected (bypass) 01101 once control register (ocr) 01110 once status register (osr) 01111 reserved (factory test control register do not access) 10000 reserved (mem_bist, do not access) 10001 C 10110 reserved (bypass, do not access) 10111 reserved (lsrl, do not access) 11000 C 11110 reserved (bypass, do not access) 11111 bypass ocr once control register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sqc w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r dr idre tme frzc rcb bcb rca bca w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MMC2001 once? debug module motorola reference manual 16-9 sqc sequential control the sqc field allows memory breakpoint b and trace occurrences to be suspended until a qualifying event occurs. this field is cleared on test logic reset. dr cpu debug request control this control bit is used to request the cpu to enter debug mode unconditionally. the cpu indicates that debug mode has been entered via the pm bits in the once status register. once the cpu enters debug mode, it returns there even with a write to the ocmr with go and ex set until the dr bit is cleared. this bit is cleared on test logic reset. idre internal debug request enable this control bit is used to enable internally generated debug requests. the internal debug request input to the once control logic (idr ) may not be used in all implemen- tations. in some implementations, the idr control input may be connected and used as an additional hardware debug request. this bit is cleared on test logic reset. 0 = disable idr input operation 1 = enable idr input operation tme trace mode enable the tme control bit enables the once trace mode operation (see 16.9 once trace logic ). this bit is cleared on test logic reset. trace operation is also affected by the sqc field described above. 0 = disable trace operation 1 = enable trace operation 7deoh6htxhqwldo&rqwuro)lhog6hwwlqjv sqc[1:0] meaning disable sequential control operation. memory breakpoints and trace operation are unaf- fected by this field. suspend normal trace counter operation until a breakpoint condition occurs for memory breakpoint b. if this mode is selected, memory breakpoint b occurrences no longer cause a breakpoint request to be generated. instead, trace counter comparisons are suspended until the first memory breakpoint b occurrence. after the first memory breakpoint b occur- rence, trace counter control is released to perform normally (assuming tme is set). this allows a sequence of breakpoint conditions to be specified prior to trace counting. qualify memory breakpoint b matches with a breakpoint occurrence for memory break- point a. if this bit is set, memory breakpoint a occurrences no longer cause a breakpoint request to be generated. instead, memory breakpoint b comparisons are suspended until the first memory breakpoint a occurrence. after the first memory breakpoint a occur- rence, memory breakpoint b is enabled to perform normally. this allows a sequence of breakpoint conditions to be specified. combine the qualifications specified by the 01 and 10 encodings of this field. in this mode, no breakpoint requests are generated, and trace count operation is enabled (if tme is set) once a memory breakpoint b occurrence follows a memory breakpoint a occurrence.
motorola once? debug module MMC2001 16-10 reference manual frzc freeze control this control bit is used in conjunction with memory breakpoint b registers to select between asserting a breakpoint condition when a memory breakpoint b occurs, or freezing the pc fifo from further updates when memory breakpoint b occurs while allowing the cpu to continue execution. the pc fifo remains frozen until the frzo bit in the osr is cleared. 0 = memory breakpoint b occurrence causes assertion of a breakpoint condition 1 = memory breakpoint b occurrence causes a freeze of pc fifo from further updates and no breakpoint assertion rcb, rca memory breakpoint b, a range control these control bits condition enabled memory breakpoints. they condition whether memory breakpoint matches will occur when a memory address falls either within the range defined by memory base address and mask, or outside the range. 0 = condition breakpoint on access within range 1 = condition breakpoint on access outside of range bcb, bca memory breakpoint b, a control these control bits enable memory breakpoints and qualify the access attributes to select whether the breakpoint match will be recognized for read, write, or instruction fetch (program space) accesses. these bits are cleared on test logic reset. see table 16-3 for the definition of the bca and bcb fields. table 16-3 memory breakpoint control field settings bc4 bc3 bc2 bc1 bc0 description 0 0 0 0 0 breakpoint disabled 0 0 0 0 1 qualify match with any access 0 0 0 1 0 qualify match with any instruction access 0 0 0 1 1 qualify match with any data access 0 0 1 0 0 qualify match with any change of flow instruction access 0 0 1 0 1 qualify match with any data write 0 0 1 1 0 qualify match with any data read 0 0 1 1 1 reserved 0 1 x x x reserved 1 0 0 0 0 reserved 1 0 0 0 1 qualify match with any user access 1 0 0 1 0 qualify match with any user instruction access 1 0 0 1 1 qualify match with any user data access 1 0 1 0 0 qualify match with any user change of flow access 1 0 1 0 1 qualify match with any user data write 1 0 1 1 0 qualify match with any user data read 1 0 1 1 1 reserved 1 1 0 0 0 reserved 1 1 0 0 1 qualify match with any supervisor access 1 1 0 1 0 qualify match with any supervisor instruction access 1 1 0 1 1 qualify match with any supervisor data access 1 1 1 0 0 qualify match with any supervisor change of flow access 1 1 1 0 1 qualify match with any supervisor data write 1 1 1 1 0 qualify match with any supervisor data read 1 1 1 1 1 reserved
MMC2001 once? debug module motorola reference manual 16-11 16.6.3 once status register (osr) the once status register (osr) is a 16-bit register used to indicate the reason(s) that debug mode was entered and the current operating mode of the cpu. these sta- tus bits are read only. figure 16-6 once status register hdro hardware debug request occurrence this read-only status bit is set when the processor enters debug mode as a result of a hardware debug request from the idr signal or the de pin. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. dro debug request occurrence this read-only status bit is set when the processor enters debug mode and the debug request (dr) control bit in the once control register is set. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. mbo memory breakpoint occurrence this read-only status bit is set when a memory breakpoint request has been issued to the cpu via the brkrq input and the cpu enters debug mode. in some situations involving breakpoint requests on instruction prefetches, the cpu may discard the request along with the prefetch. in this case, this bit may become set due to the cpu entering debug mode for another reason. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. swo software debug occurrence this read-only status bit is set when the processor enters debug mode of operation as a result of the execution of the bkpt instruction. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. to trace count occurrence this read-only status bit is set when the trace counter reaches zero with the trace mode enabled and the cpu enters debug mode. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. frzo fifo freeze occurrence this read-only status bit is set when a fifo freeze occurs. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. sqb sequential breakpoint b arm occurrence this read-only status bit is set when sequential operation is enabled and a memory breakpoint b event has occurred to enable trace counter operation. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. osr once status register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 hdro dro mbo swo to frzo sqb sqa pm w reset: 0 0 0 0 0 0 0 0 0 0
motorola once? debug module MMC2001 16-12 reference manual sqa sequential breakpoint a arm occurrence this read-only status bit is set when sequential operation is enabled and a memory breakpoint a event has occurred to enable memory breakpoint b operation. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. pm processor mode these status bits indicate the processor operating mode. they allow coordination of the once controller with the cpu to synchronize the two. 16.7 once decoder (odec) the once decoder (odec) receives as input the 8-bit command from the ocmr and status signals from the processor. the odec generates all the strobes required for reading and writing the selected once registers. 16.8 memory breakpoint logic memory breakpoints can be set for a particular memory location or on accesses within an address range. the breakpoint logic contains an input latch for addresses, registers that store the base address and address mask, comparators, attribute qual- ifiers, and a breakpoint counter. figure 16-7 illustrates the basic functionality of the once memory breakpoint logic. this logic is duplicated to provide two independent breakpoint resources. address comparators can be used to determine where a program may be getting lost or when data is being written to areas which should not be written. they are also use- ful in halting a program at a specific point to examine or change registers or memory. using address comparators to set breakpoints enables the user to set breakpoints in ram or rom in any operating mode. memory accesses are monitored according to the contents of the ocr. 7deoh3urfhvvru0rgh)lhog6hwwlqjv pm[1:0] meaning 00 processor in normal mode 01 processor in stop, doze, or wait mode 10 processor in debug mode 11 reserved
MMC2001 once? debug module motorola reference manual 16-13 figure 16-7 once memory breakpoint logic the address comparator generates a match signal when the address on the bus matches the address stored in the breakpoint address base register, as masked with individual bit masking capability provided by the breakpoint address mask register. the address match signal and the access attributes are further qualified with the rcx and bcx[4:0] control bits. this qualification is used to decrement the breakpoint counter conditionally if its contents are non-zero. if the contents are zero, the counter is not decremented and the breakpoint event occurs (isbkptx asserted). 16.8.1 memory address latch (mal) the memory address latch (mal) is a 32-bit register that latches the address bus on every access. addr[31:0] attr address base register x address comparator dsi dso dsck 0$7&+ %&>@5&[ dec breakpoint count=0 isbkptx occurred breakpoint counter memory breakpoint qualification memory address latch address mask register x match
motorola once? debug module MMC2001 16-14 reference manual 16.8.2 breakpoint address base registers (baba, babb) the 32-bit breakpoint address base registers (baba, babb) store memory break- point base addresses. baba and babb can be read or written through the once serial interface. before enabling breakpoints, the external command controller should load these registers. 16.8.3 breakpoint address mask registers (bama, bamb) the 32-bit breakpoint address mask registers (bama, bamb) store memory break- point base address masks. bama and bamb can be read or written through the once serial interface. before enabling breakpoints, the external command controller should load these registers. 16.8.4 breakpoint address comparators the breakpoint address comparators are not externally accessable. each compares the memory address stored in mal with the contents of babx, as masked by bamx, and signals the control logic when a match occurs. 16.8.5 memory breakpoint counters (mbca, mbcb) the 16-bit memory breakpoint counter x (mbcx) register is loaded with a value equal to the number of times, minus one, that a memory access event should occur before a memory breakpoint is declared. the memory access event is specified by the rcx and bcx[4:0] bits in the ocr register and by the memory base and mask registers. on each occurrence of the memory access event, the breakpoint counter, if currently non-zero, is decremented. when the counter has reached the value of zero and a new occurrence takes place, the isbkptx signal is asserted and causes the cpus brkrq input to be asserted. the mbcx can be read or written through the once serial interface. anytime the breakpoint registers are changed, or a different breakpoint event is selected in the ocr, the breakpoint counter must be written afterward. this assures that the once breakpoint logic is reset and that no previous events will affect the new breakpoint event selected. 16.9 once trace logic the once trace logic allows the user to execute instructions in single or multiple steps before the device returns to debug mode and awaits once commands from the debug serial port. (the once trace logic is independent of the m?core trace facility, which is controlled through the trace mode bits in the m?core processor status reg- ister). the once trace logic block diagram is shown in figure 16-8 .
MMC2001 once? debug module motorola reference manual 16-15 figure 16-8 once trace logic block diagram 16.9.1 trace counter (otc) the trace counter (otc) allows more than one instruction to be executed in real time before the device returns to debug mode. this feature helps the software developer debug sections of code that are time-critical. the trace counter also enables the user to count the number of instructions executed in a code segment. the otc is a 16-bit counter that can be read, written, or cleared through the once serial interface. if n instructions are to be executed before entering debug mode, the trace counter should be loaded with nC1. n must not equal zero unless the sequential breakpoint control capability described in 16.6.2 once control register (ocr) is being used. in this case a value of zero (indicating a single instruction) is allowed. the trace counter is cleared by hardware reset. 16.9.2 trace operation the following steps initiate trace mode operation: 1. load the counter with a value. this value must be non-zero, unless the sequential breakpoint control capability described in 16.6.2 once control register (ocr) is being used. in this case a value of zero (indicating a single instruction) is allowed. 2. initialize the program counter and instruction register in the cpuscr with values corresponding to the start location of the instruction(s) to be executed real-time. 3. set the tme bit in the ocr. 4. release the processor from debug mode by executing the appropriate command issued by the external command controller. when debug mode is exited, the counter is decremented after each execution of an instruction. interrupts can be serviced, and all instructions executed (including inter- rupt services) will decrement the trace counter. dsi dso dsck dec end of instruction count=0 istrace trace counter
motorola once? debug module MMC2001 16-16 reference manual when the trace counter decrements to zero, the once control logic requests that the processor re-enter debug mode, and the trace occurrence bit to in the osr is set to indicate that debug mode has been requested as a result of the trace count function. the trace counter allows a minimum of two instructions to be specified for execution prior to entering trace (specified by a count value of one), unless the sequential breakpoint control capability described in 16.6.2 once control register (ocr) is being used. in this case a value of zero (indicating a single instruction) is allowed. 16.10 methods of entering debug mode the osr indicates that the cpu has entered debug mode via the pm status field. the following paragraphs discuss conditions that invoke debug mode. 16.10.1 debug request during reset when the dr bit in the ocr is set, assertion of reset causes the device to enter debug mode. in this case the device may fetch the reset vector and the first instruc- tion of the reset exception handler but does not execute an instruction before entering debug mode. 16.10.2 debug request during normal activity setting the dr bit in the ocr during normal device activity causes the device to fin- ish the execution of the current instruction and then enter debug mode. note that in this case the device completes the execution of the current instruction and stops after the newly fetched instruction enters the cpu instruction latch. this process is the same for any newly fetched instruction, including instructions fetched by interrupt pro- cessing or those that will be aborted by interrupt processing. 16.10.3 debug request during stop, doze, or wait mode setting the dr bit in the ocr when the device is in stop, doze, or wait mode (i. e., has executed a stop, doze, or wait instruction) causes the device to exit the low- power state and enter the debug mode. note that in this case, the device completes the execution of the stop, doze, or wait instruction and halts after the next instruction enters the instruction latch. 16.10.4 software request during normal activity executing the bkpt instruction when the fdb (force debug enable mode) control bit in the control state register is set, causes the cpu to enter debug mode after the instruction following the bkpt instruction has entered the instruction latch. 16.10.5 enabling once trace mode when the once trace mode mechanism is enabled and the trace count is greater than zero, the trace counter is decremented for each instruction executed. complet- ing execution of an instruction when the trace counter is zero causes the cpu to enter debug mode.
MMC2001 once? debug module motorola reference manual 16-17 note 2qo\ lqvwuxfwlrqv dfwxdoo\ h[hfxwhg fdxvh wkh wudfh frxqwhu wr ghfuh phqwlhdqderuwhglqvwuxfwlrqgrhvqrwghfuhphqwwkhwudfhfrxqwhu dqggrhvqrwlqyrnhghexjprgh 16.10.6 enabling once memory breakpoints when the once memory breakpoint mechanism is enabled with a breakpoint counter value of zero, the device enters debug mode after completing the execution of the instruction that caused the memory breakpoint to occur. in case of breakpoints on instruction fetches, the breakpoint is acknowledged immediately after the execution of the fetched instruction. in case of breakpoints on data memory addresses, the breakpoint is acknowledged after the completion of the memory access instruction. 16.11 pipeline information and write-back bus register a number of on-chip registers store the cpu pipeline status and are configured in a single scan chain for access by the once controller. the cpuscr once register contains these processor resources, which are used to restore the pipeline and resume normal device activity upon return from debug mode. these resources also provide a mechanism for the emulator software to access processor and memory contents. figure 16-9 shows the block diagram of the pipeline information registers contained in the cpuscr. figure 16-9 cpu scan chain register (cpuscr) tdo tdi tck pc psr ir ctl wbbr 32 32 16 16 31 0 31 0 31 0 15 0 15 0
motorola once? debug module MMC2001 16-18 reference manual 16.11.1 program counter register (pc) the once program counter register (pc) is a 32-bit latch that stores the value in the cpu program counter when the device enters debug mode. the cpu pc is affected by operations performed during debug mode and must be restored by the external command controller when the cpu returns to normal mode. 16.11.2 instruction register (ir) the instruction register (ir) provides a mechanism for controlling the debug session. the ir allows the debug control block to execute selected instructions; the debug control module provides single-step capability. when scan-out begins, the ir contains the opcode of the next instruction to be exe- cuted at the time debug mode was entered. this opcode must be saved in order to resume normal execution at the point debug mode was entered. on scan-in, the ir can be filled with an opcode selected by debug control software in preparation for exiting debug mode. selecting appropriate instructions allows a user to examine or change memory locations and processor registers. once the debug session is complete and normal processing is to be resumed, the ir can be loaded with the value originally scanned out. 16.11.3 control state register (ctl) the control state register (ctl) is used to set control values when debug mode is exited. on scan-in, this register is used to control specific aspects of the cpu. certain bits reflect internal processor status and should be restored to their original values. the ctl is a 16-bit latch that stores the value of certain internal cpu state variables before debug mode is entered. this register is affected by the operations performed during the debug session and should be restored by the external command controller when returning to normal mode. in addition to saved internal state variables, the bits are used by emulation firmware to control the debug process. reserved bits represent the internal processor state. restore these bits to their origi- nal value after a debug session is completed, i.e., when a once command is issued with the go and ex bits set and not ignored. set these bits to ones while instructions are executed during a debug session. figure 16-10 control state register ctl control state register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r reserved ffy fdb sz tc reserved w reset: 0 0 0 0 0 0 0
MMC2001 once? debug module motorola reference manual 16-19 ffy feed forward y operand this control bit is used to force the content of the wbbr to be used as the y operand value of the first instruction to be executed following an update of the cpuscr. this gives the debug firmware the capability of updating processor registers by initializing the wbbr with the desired value, setting the ffy bit, and executing a mov instruc- tion to the desired register. fdb force psr debug enable mode setting this control bit places the processor in debug enable mode. in debug enable mode, execution of the bkpt instruction as well as recognition of the brkrq input causes the processor to enter debug mode, as if the dbgrq input had been asserted. sz prefetch size this control field is used to drive the cpu siz[1:0] outputs on the first instruction prefetch caused by issuing a once command with the go bit set and not ignored. it should be set to indicate a 16-bit size, i.e., 0b10. this field should be restored to its original value after a debug session is completed, i.e., when a once command is issued with the go and ex bits set and not ignored. tc prefetch transfer code this control field is used to drive the cpu tc[2:0] outputs on the first instruction prefetch caused by issuing a once command with the go bit set and not ignored. it should typically be set to indicate a supervisor instruction access, i.e., 0b110. this field should be restored to its original value after a debug session is completed, i.e., when a once command is issued with the go and ex bits set and not ignored. 16.11.4 write-back bus register (wbbr) the write-back bus register (wbbr) is used as a means of passing operand informa- tion between the cpu and the external command controller. whenever the external command controller needs to read the contents of a register or memory location, it forces the device to execute an instruction that brings that information to wbbr. for example, to read the content of processor register r0 , a mov r0,r0 instruction is executed, and the result value of the instruction is latched into the wbbr. the con- tents of wbbr can then be delivered serially to the external command controller. to update a processor resource, this register is initialized with a data value to be writ- ten, and a mov instruction is executed which uses this value as a write-back data value. the ffy bit in the control state register forces the value of the wbbr to be substituted for the normal source value of a mov instruction, thus allowing updates to processor registers to be performed. 16.11.5 processor status register (psr) the once processor status register (psr) is a 32-bit latch used to read or write the m?core processor status register. whenever the external command controller needs to save or modify the contents of the m?core processor status register, this register is used. this register is affected by the operations performed in debug mode and must be restored by the external command controller when returning to normal mode.
motorola once? debug module MMC2001 16-20 reference manual 16.12 instruction address fifo buffer (pc fifo) to ease debugging activity and keep track of program flow, a first-in-first-out (fifo) buffer stores the addresses of the last eight instruction change-of-flow prefetches that were issued. the fifo is implemented as a circular buffer containing eight 32-bit registers and one 3-bit counter. all the registers have the same address, but any read access to the fifo address causes the counter to increment and point to the next fifo register. the registers are serially available to the external command controller through the common fifo address. figure 16-11 shows the block diagram of the pc fifo. figure 16-11 once pc fifo pc fifo register 0 tdo tck pc fifo register 1 pc fifo register 2 pc fifo register 3 pc fifo register 4 instruction fetch address circular buffer pointer pc fifo shift register pc fifo register 5 pc fifo register 6 pc fifo register 7
MMC2001 once? debug module motorola reference manual 16-21 the fifo is not affected by operations performed in debug mode, except for incre- menting the fifo pointer when the fifo is read. when debug mode is entered, the fifo counter points to the fifo register containing the address of the oldest of the eight change-of-flow prefetches. the first fifo read obtains the oldest address, and the following fifo reads return the other addresses from the oldest to the newest (in order of execution). to ensure fifo coherence, a complete set of eight reads of the fifo must be per- formed. each read increments the fifo pointer, causing it to point to the next loca- tion. after eight reads, the pointer points to the same location as before the start of the read procedure. 16.12.1 reserved test control registers (reserved, mem_bist, ftcr, lsrl) these registers are reserved for factory testing. warning to prevent damage to the device or system, do not access these registers during normal operation. 16.13 serial protocol description the following protocol permits an efficient means of communication between the once external command controller and the MMC2001. before starting any debug- ging activity, the external command controller must wait for an acknowledgment that the device has entered debug mode. the external command controller communi- cates with the device by sending 8-bit commands to the once command register and 16 to 128 bits of data to one of the other once registers. both commands and data are sent or received lsb first. after sending a command, the external command con- troller must wait for the processor to acknowledge execution of certain commands before it can properly access another once register. 16.13.1 once commands the once commands can be classified as follows: ? read commands (the device delivers the required data) ? write commands (the device receives data and writes the data in one of the once registers) ? commands that do not have data transfers associated with them. the commands are eight bits long and have the format shown in figure 16-4 . 16.14 target site debug system requirements a typical debug environment consists of a target system in which the MMC2001 resides in the user-defined hardware.
motorola once? debug module MMC2001 16-22 reference manual the external command controller acts as the medium between the MMC2001 target system and a host computer. the external command controller circuit acts as a serial debug port driver and host computer command interpreter. the controller issues commands based on the host computer inputs from a user interface program which communicates with the user. 16.15 interface connector for jtag/once serial port figure 16-12 shows the recommended connector pinout and interface requirements for debug controllers that access the jtag/once port. the connector has two rows of seven pins with 0.1 inch center-to-center spacing between pins in each row and each column. figure 16-12 recommended connector interface to jtag/once port tdi tdo tclk gpio/si target_reset key (no connect) gnd 12 34 56 78 910 10 k w 10 k w top view 11 12 13 14 target vdd gpio/so dbev (0.1 inch center-to-center) 10 k w 10 k w target vdd target vdd trst 10 k w tms 10 k w note: gpio/si and gpio/so are not required for once operation at this time. these pins can be used for high speed downloads with a recommended interface. 10 k w wired or with target reset circuit. this signal must be able to assert/monitor system reset.
MMC2001 electrical characteristics motorola reference manual a-1 preliminary appendix a electrical characteristics this section contains preliminary information on dc/ac electrical characteristics and ac timing specifications of the MMC2001. a.1 maximum ratings a.2 dc electrical specifications table a-1 maximum ratings rating symbol value unit internal supply voltage v cci C0.3 to + 4.5 v external supply voltage v cce C0.3 to + 4.5 v operating temperature range t a C40 to + 85 c storage temperature t stg C55 to + 150 c table a-2 dc electrical specifications characteristic symbol min max unit internal supply voltage v cci 1.8 3.6 v external supply voltage v cce v cci 3.6 v battery supply voltage v ccb v cce C 1.0 v cce v input high voltage v ih 0.7 * v cce v cce + 0.2 v input low voltage v il C0.3 0.2 * v cce v input leakage current (all input only pins) i in C10 10 m a hi-z (off state) leakage current (all input, non-crystal outputs, and i/o pins) i oz C10 10 m a signal low input current (tms, tdi, tck, trst , de , row[7:0]) i l C0.015 0.2 ma signal high input current, (tms, tdi, tck, trst , de , row[7:0]) i h C0.015 0.2 ma output high voltage, i oh = 0.4 ma v oh 0.75 * v cce v cce v output low voltage, i ol = 0.8 ma v ol 0 0.18 * v cce v v ccb standby current (lvrstin asserted) v cci supply current at 2.0 v @ 34 mhz stop doze wait run ibatt_standby i cc_stop i cc_doze i cc_wait i cc_run 3 60 3 3 40 m a m a ma ma ma pin capacitance c in 10pf load capacitance c l 50pf
motorola electrical characteristics MMC2001 a-2 reference manual preliminary a.3 clock input specifications figure a-1 clkin timing (for square wave input) a.4 ac electrical specifications the following ac electrical specifications are given for v cci = 2.0 +/C 10% and v cce = 3.3 v +/C 10% with a maximum capacitive load of 50 pf on the outputs. a.4.1 reset, mod timing specifications table a-3 clock input specifications num characteristic symbol min max unit clkin frequency 1 notes: 1. clkin is an ac-coupled input requiring a periodic waveform, either a sine wave or a square wave. the dc bias level must keep the minimum level of the signal greater than gnd and the maximum level of the signal less than v cce . clk 8 34 mhz 1 clkin period t hrc 29.4 ns 2 clkin rise time (for square wave input) 3 ns 3 clkin fall time (for square wave input) 3 ns clkin duty cycle 45 55 % clkin input voltage 0.8 v cce vpp crystal frequency 32.768 khz crystal period t lrc 30.5 m s table a-4 reset, mod timing specifications num characteristic expression min max unit 11 rstin duration to be qualified as valid 4*t lrc + 0.05 122.12 m s 12 delay from rstin assertion to rstout assertion min: 4.5 * t lrc max: 5.5 * t lrc 137.33 167.85 m s 13 delay from rstin negation to rstout negation 8 * t lrc 244.14 m s 14 delay from rstin assertion to all pins at reset value (periodically sampled and not 100% tested) min: 4.5 * t lrc max: 5.5 * t lrc 137.33 167.85 m s 15 mod setup time to rstout negation 4*t lrc + 0.05 122.12 m s 16 mod hold time 0 ns clkin 1 2 3
MMC2001 electrical characteristics motorola reference manual a-3 preliminary figure a-2 reset timing figure a-3 mod timing a.4.2 external interrupt timing specifications table a-5 external interrupt timing specifications num characteristic symbol min max unit 21 minimum edge-triggered intn width high 2 * t hrc +2 60.8 ns 22 minimum edge-triggered intn width low 2 * t hrc +2 60.8 ns rstin all pins rstout 11 12 14 reset value 13 rstout mod 15 16
motorola electrical characteristics MMC2001 a-4 reference manual preliminary figure a-4 external interrupt timing a.4.3 eim timing specifications table a-6 eim timing specifications 1 notes: 1. output timing is measured at the pin. the specifications assume a capacitive load of 50 pf. num characteristic min max unit 31 clkout rise to address, r/w valid 0 27 ns 32 clkout rise to address, r/w invalid (output hold) 0 ns 33 clkout rise to cs asserted 0 29 ns 34 clkout rise to cs negated (output hold) 0 ns 35 clkout fall to oe , eb asserted (read, oea=0), eb asserted (write) 2 2. eb outputs are asserted for reads if the ebc bit in the corresponding cs control register is cleared . 016ns 36 clkout rise to oe , eb asserted (read, oea=1) 2 016ns 37 clkout rise to oe , eb negated (output hold) (read) 2 0ns 37 clkout rise to eb negated (output hold) (write, wen=0) 0 ns 38 clkout fall to eb negated (output hold) (write, wen=1) 0 ns 39 clkout fall to oe , eb asserted (wsc=0) 2 013ns 40 clkout rise to oe , eb negated (output hold) (wsc=0) 2 0ns 41 data in valid to clkout rise (setup) 17 ns 42 clkout rise to data in invalid (hold) 0 ns 43 clkout rise to data out valid (wsc>0) 15 ns 44 clkout rise to data out invalid (output hold) (wsc>0) 0 ns 45 clkout rise to data out high impedance (wsc>0) 15 ns 46 clkout fall to data out valid (wsc=0) 17 ns 47 clkout rise to data out invalid (output hold) (wsc=0) 0 ns 48 clkout rise to data out high impedance (wsc=0) 17 ns intn intn 21 22
MMC2001 electrical characteristics motorola reference manual a-5 preliminary figure a-5 eim read/write timing clkout 34 33 address 41 data in (read) data out (wsc>0) (write) 43 45 cs oe , eb (wsc=0) 42 44 40 39 32 31 oe , eb 37 35 (oea=0) oe , eb (oea=1) 37 36 eb (wen=1) 38 35 46 data out (write) 47 (wsc=0) r/w 48 eb 37 35 (wen=0) (read) (read) (write) (write)
motorola electrical characteristics MMC2001 a-6 reference manual preliminary a.4.4 ispi timing specifications table a-7 ispi timing specifications num characteristic symbol min max unit operating frequency (sclk) f op(s) dc 1/8 clk 51 cycle time t cyc 8 1024 clk 52 enable lead time pha=0 pha=1 t lead 1 1 sclk 53 enable lag time pha=0 pha=1 t lag 1 1 1 1 sclk 54 clock (sclk) high time t w(sckh) 4 512 clk 55 clock (sclk) low time t w(sckl) 4 512 clk 56 data setup time (inputs) t su 8ns 57 data hold time (inputs) t h 8ns 58 access time slave t a 1sclk 59 disable time (hold time) t dis 1sclk 60 data valid (after enable edge) t v(s) 5ns 61 data hold time (output) (after enable edge) t ho 0ns 62 rise time (20% v dd to 70% v dd , c l = 20pf) manual/interval mode slave mode t rs 10 10 ns 63 fall time (20% v dd to 70% v dd , c l = 20pf) manual/interval mode slave mode t fs 0 0 10 10 ns 64 sequential transfer delay 1 notes: 1. signal depends on software in interval mode. t bt 1sclk
MMC2001 electrical characteristics motorola reference manual a-7 preliminary figure a-6 spi slave timing (pha = 0) figure a-7 spi slave timing (pha = 1) spi_en (input) sclk (input, pol=0) sclk (input, pol=1) spi_miso (output) spi_mosi (input) msb out data lsb out msb in data lsb in note: pd port data is not defined, but normally lsb of character previously transmitted (likely not to be lsb in slave mode). 55 54 51 54 55 62 63 63 62 53 56 60 61 msb out msb in 64 52 61 pd 59 58 60 spi_en (input) sclk (input, pol=0) sclk (input, pol=1) spi_miso (output) spi_mosi (input) msb out data lsb out msb in data lsb in note: pd port data is not defined, but normally lsb of character previously transmitted (likely not to be lsb in slave mode). 54 55 51 55 54 63 62 62 63 53 56 60 61 59 57 msb out msb in 64 pd pd 58
motorola electrical characteristics MMC2001 a-8 reference manual preliminary figure a-8 spi manual/interval mode timing (pha = 0) figure a-9 spi manual/interval mode timing (pha = 1) spi_en (output, spi_en (output, sns=0) sclk (output, pol=0) sclk (output, pol=1) spi_mosi (output) spi_miso (input) msb out data lsb out msb in data lsb in 55 54 51 54 55 62 63 63 53 pd* 56 60 61 57 msb out msb in 64 52 61 tbd tbd note: the sequential transfer delay is determined by the settings in the spi interval control register. note 62 sns=1) spi_en (output, spi_en (output, sns=0) sclk (output, pol=0) sclk (output, pol=1) spi_mosi (output) spi_miso (input) msb out data lsb out tbd msb in data lsb in 54 55 59 55 54 63 62 62 63 53 pd* 56 60 tbd 61 52 57 msb out msb in 64 note: the sequential transfer delay is determined by the settings in the spi interval control register. note 51 sns=1)
MMC2001 electrical characteristics motorola reference manual a-9 preliminary a.4.5 once timing specifications figure a-10 test clock input timing figure a-11 trst timing table a-8 once timing specifications num characteristic min max unit tck frequency of operation 0 clk/2 mhz 92 tck clock pulse width measured at 1.5 v 20 ns 93 tck rise and fall times 0 8 ns 94 tms, tdi data setup time 7 ns 95 tms, tdi data hold time 25 ns 96 tck low to tdo data valid 0 44 ns 97 tck low to tdo high z 0 44 ns 98 trst assert time 100 ns 99 trst setup time to tck low 40 ns tck v ih v il 92 92 93 93 tck trst 98 99
motorola electrical characteristics MMC2001 a-10 reference manual preliminary figure a-12 test access port timing tck tdi tdo tdo tdo v ih v il input data valid output data valid output data valid tms 96 94 95 97 96
MMC2001 packaging and pin assignments motorola reference manual b-1 appendix b packaging and pin assignments b.1 overview the following diagram shows the pin assignments of the MMC2001. figure b-1 144-lead plastic thin quad flat pack pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 cs0 cs1 cgnd cvdd cs2 cs3 eb0 eb1 tdo de tms tdi tck trst test qgnd qvcch qvcc int7 int6 int5 int4 int3 ggnd0 col4 gvdd0 int2 int1 int0 col7 col6 col5 col3 col2 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 MMC2001 top view oe r/w data10 data9 data8 data7 data6 data5 data4 dgnd0 dvdd0 data3 data2 data1 data0 qgnd qvcch qvcc xvdd mod xgnd xosc exosc xgnd not used* vstby fvdd vbatt lvrstin rstin rstout fgnd clkin clkout gpsout if data11 dvdd1 ggnd1 col0 row7 row6 row5 row4 row3 row2 row1 row0 spi_miso hvdd hgnd spi_mosi spi_en spi_clk qvcch spi_gp txd0/pstat0 rxd0/pstat1 rts0 /pstat2 cts0 /pstat3 qvcc qgnd pwm3 txd1/siz0 rxd1/siz1 jvdd jgnd pwm0 pwm1 pwm2 pwm4 pwm5 gvdd1 col1 addr19 addr18 avdd2 agnd2 addr17 addr16 addr15 addr14 addr13 addr12 addr11 avdd1 agnd1 addr10 addr9 qvcch addr8 addr7 addr6 addr5 addr4 avdd0 qvcc qgnd data13 agnd0 addr3 addr2 addr1 addr0 data15 data14 data12 dgnd1 addr20 addr21 *pin 12 must be grounded for proper operation but is not a system ground.
motorola packaging and pin assignments MMC2001 b-2 reference manual
MMC2001 programming reference motorola reference manual c-1 appendix c programming reference c.1 peripheral module address assignment the register maps of all peripheral devices for MMC2001 are located on 4096-byte boundaries. table c-1 defines the address assignment for the on-chip components. table c-1 MMC2001 address map address range (hex) use access 00000000 C 0003ffff on-chip rom array supervisor, selective user 00040000 C 000fffff rom echoes supervisor, selective user 00100000 C 0fffffff not used (access causes transfer error) 10000000 C 10000fff interrupt controller supervisor only 10001000 C 10001fff timer/reset unit supervisor only 10002000 C 10002fff not used (access causes transfer error) 10003000 C 10003fff keypad port supervisor only 10004000 C 10004fff external interface module supervisor only 10005000 C 10005fff pulse-width modulator supervisor only 10006000 C 10006fff not used (access causes transfer error) 10007000 C 10007fff gpio edge port supervisor only 10008000 C 10008fff interval spi supervisor only 10009000 C 10009fff uart 0 supervisor only 1000a000 C 1000afff uart 1 supervisor only 1000b000 C 1fffffff not used (access causes transfer error) 20000000 C 2fffffff external devices supervisor, selective user 30000000 C 30007fff on-chip ram array supervisor, selective user 30008000 C 3000ffff ram echoes supervisor, selective user 30100000 C 40000000 not used (access causes transfer error)
motorola programming reference MMC2001 c-2 reference manual c.2 interrupt controller programming model control and status registers for the interrupt controller begin at address 0x40002000. c.2.1 interrupt source register (intsrc) access the 32-bit interrupt source register with 32-bit loads only. figure c-1 interrupt source register inx interrupt source x this bit indicates the state of the corresponding interrupt source. 0 = negated 1 = asserted bits [0:2] of this register are tied to logic level one to allow software to schedule inter- rupts by enabling one or more of these sources in the appropriate interrupt enable register(s) (nier, fier). c.2.2 normal interrupt enable register (nier) access the 32-bit normal interrupt enable register with 32-bit loads and stores only. table c-2 interrupt controller address map address use access 10000000 interrupt source register (intsrc) supervisor only 10000004 normal interrupt enable register (nier) supervisor only 10000008 fast interrupt enable register (fier) supervisor only 1000000c normal interrupt pending register (nipnd) supervisor only 10000010 fast interrupt pending register (fipnd) supervisor only intsrc interrupt source register 10000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 in31 in30 in29 in28 in27 in26 in25 in24 in23 in22 in21 in20 in19 in18 in17 in16 reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 in15 in14 in13 in12 in11 in10 in9 in8 in7 in6 in5 in4 in3 1 1 1 reset:
MMC2001 programming reference motorola reference manual c-3 figure c-2 normal interrupt enable register enx enable normal interrupt flag x this bit enables the corresponding interrupt source to request a normal interrupt. 0 = disable 1 = enable a reset operation clears this bit. when the enable flag is set and the corresponding interrupt line is asserted, the inter- rupt controller asserts a normal interrupt request. enabling an interrupt source which has an asserted request causes that interrupt to become pending, and a request to the cpu is asserted if not already outstanding. c.2.3 fast interrupt enable register (fier) access the 32-bit fast interrupt enable register with 32-bit loads and stores only. figure c-3 fast interrupt enable register efx enable fast interrupt flag x this bit enables the corresponding interrupt source to request a fast interrupt. 0 = disable 1 = enable a reset operation clears this bit. nier normal interrupt enable register 10000004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 en31 en30 en29 en28 en27 en26 en25 en24 en23 en22 en21 en20 en19 en18 en17 en16 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en15 en14 en13 en12 en11 en10 en9 en8 en7 en6 en5 en4 en3 en2 en1 en0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fier fast interrupt enable register 10000008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ef31 ef30 ef29 ef28 ef27 ef26 ef25 ef24 ef23 ef22 ef21 ef20 ef19 ef18 ef17 ef16 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ef15 ef14 ef13 ef12 ef11 ef10 ef9 ef8 ef7 ef6 ef5 ef4 ef3 ef2 ef1 ef0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola programming reference MMC2001 c-4 reference manual when the enable flag is set and the corresponding interrupt line is asserted, the inter- rupt controller asserts a fast interrupt request. enabling an interrupt source that has an asserted request causes that interrupt to become pending, and a request to the cpu is asserted if not already outstanding. c.2.4 normal interrupt pending register (nipnd) access the 32-bit normal interrupt pending register with 32-bit loads only. figure c-4 normal interrupt pending register npx normal interrupt pending flag x this bit indicates a pending normal interrupt request from the corresponding interrupt source. 0 = no request 1 = interrupt request pending when a normal interrupt enable flag is set and the corresponding interrupt line is asserted, the interrupt controller asserts a normal interrupt request. the normal inter- rupt pending flags reflect the interrupt input lines which are asserted and are currently enabled to generate a normal interrupt. c.2.5 fast interrupt pending register (fipnd) access the 32-bit read-only fast interrupt pending register with 32-bit loads only. figure c-5 fast interrupt pending register nipnd normal interrupt pending register 1000000c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 np31 np30 np29 np28 np27 np26 np25 np24 np23 np22 np21 np20 np19 np18 np17 np16 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 np15 np14 np13 np12 np11 np10 np9 np8 np7 np6 np5 np4 np3 np2 np1 np0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fipnd fast interrupt pending register 10000010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 fp31 fp30 fp29 fp28 fp27 fp26 fp25 fp24 fp23 fp22 fp21 fp20 fp19 fp18 fp17 fp16 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fp15 fp14 fp13 fp12 fp11 fp10 fp9 fp8 fp7 fp6 fp5 fp4 fp3 fp2 fp1 fp0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MMC2001 programming reference motorola reference manual c-5 fpx fast interrupt pending flag x this bit indicates a pending fast interrupt request from the corresponding interrupt source. 0 = no request 1 = interrupt request pending when a fast interrupt enable flag is set and the corresponding interrupt line is asserted, the interrupt controller will assert a fast interrupt request (fint cpu input). the fast interrupt pending flags reflect the interrupt input lines which are currently enabled to generate a fast interrupt and are asserted. c.3 timer/reset programming model table c-3 shows the timer/reset module address map. c.3.1 reset source/chip configuration register (rscr) this status and control register gives the state of the reset sources and serves to control the clkout pin. writes to this register clear any previously set status bits. access this register with 32-bit loads and stores only. table c-3 timer/reset module address map address use access 10001000 reset source/chip configuration register (rscr) supervisor only 10001004 time-of-day control/status register (todcsr) supervisor only 10001008 time-of-day seconds register (todsr) supervisor only 1000100c time-of-day fraction register (todfr) supervisor only 10001010 time-of-day seconds alarm register (todsar) supervisor only 10001014 time-of-day fraction alarm register (todfar) supervisor only 10001018 reserved supervisor only 1000101c watchdog control register (wcr) supervisor only 10001020 watchdog service register (wsr) supervisor only 10001024 interval timer control/status register (itcsr) supervisor only 10001028 pit data register (itdr) supervisor only 1000102c pit alternate data register (itadr) supervisor only 1000102e to 10001fff reserved supervisor only 10002000 to 10002fff not used (access causes transfer error) not applicable
motorola programming reference MMC2001 c-6 reference manual * = see bit description figure c-6 reset source register ckos clkout source this bit controls the clock source for the clkout pin. modify this pin only when the clock output has been disabled. this bit is cleared by por, a qualified assertion of the rstin pin, or a qualified assertion of the lvrstin pin. 0 = clkout source is hi_refclk 1 = clkout source is low_refclk ckoe clkout enable this bit controls the drive enable for the clkout pin. it is cleared by por, a quali- fied assertion of the rstin pin, or a qualified assertion of the lvrstin pin. 0 = clkout is disabled and forced to the low state 1 = clkout is enabled and driven from the source selected by ckos lvrstin lvrstin pin this bit is set when the lvrstin pin is asserted to reset the MMC2001. it is not affected by the other reset sources. when the por bit is set, however, this bit is undefined. this bit is cleared by writing to rscr. rst rstin pin this bit is set when the rstin pin is asserted and qualified by the four-cycle qualifier to reset the MMC2001. it is not affected by the other reset sources. when the por bit is set, however, this bit is undefined. it is cleared by writing to rscr. por power-on reset this bit is set when an internal por occurs to reset the chip. it is not affected by the other reset sources. it is cleared by writing to rscr. wdr watchdog reset this bit is set when the watchdog timer expires. it is cleared by por, a qualified assertion of the rstin pin, a qualified assertion of the lvrstin pin, or by writing to rscr. rscr reset source/chip configuration register 10001000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 0000 ckos ckoe 0000 lvrst in rst por wdr w reset: 0* 0* * * * 0*
MMC2001 programming reference motorola reference manual c-7 c.3.2 time-of-day control/status register (todcsr) figure c-7 tod control/status register access this register with 32-bit loads and stores only. ae alarm enable this bit controls the function of the tod alarm 0 = alarm function is off to save power 1 = alarm function is on aie alarm interrupt enable this bit controls the alarm interrupt function 0 = aif is inhibited from reaching the cpu 1 = aif is allowed to request an interrupt aif alarm interrupt flag this read-only bit is the alarm interrupt flag. it is cleared by writing to the tod fraction alarm register (todfar). 0 = no alarm interrupt is present 1 = alarm interrupt is present c.3.3 tod seconds register (todsr) the time-of-day seconds register is a 32-bit read/write register that holds the number of elapsed seconds. it is clocked by a 1-hz signal generated as a carry from the tod fraction register. when todsr is read, the content of the fraction counter is latched into a holding buffer to be read later. this prevents a fraction rollover between reads of the two registers from causing incorrect data to be read. when todsr is written, the todfr is cleared to all zeros. todsr is not affected by the watchdog reset or by a reset initiated by the external reset signal, but is undefined after a por. access this register with 32-bit loads and stores only. todcsr time-of-day control/status register 10001004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 ae aie aif w reset: 0 0 0
motorola programming reference MMC2001 c-8 reference manual figure c-8 tod seconds register c.3.4 tod fraction register (todfr) the 32-bit time-of-day fraction register holds eight bits of data that represent the binary fraction of a second. it is clocked by the 32.768-khz low_refclk divided by 128 (256 hz). reads of this register return the value latched when the tod seconds register was previously read. continuous reads return the same value until the todsr is read and new data is latched from the fraction counter. these eight bits are cleared whenever the todsr is written but are not affected by either reset pin or the watchdog reset conditions. the fraction counter is undefined after a por. writes to this register cause all eight bits to be set. access this register with 32-bit accesses only. figure c-9 tod fraction register c.3.5 tod seconds alarm register (todsar) the time-of-day seconds alarm register is a 32-bit read/write register which holds data (in seconds) to be compared to the tod seconds register. the comparison is made every 1/256 of a second if the alarm function is enabled by the ae bit in the todcsr. writes to this register inhibit alarm compares until the todfar is written. for proper alarm operation, the fraction alarm register must be (re)written after a write to this register. this register is not affected by any of the reset conditions. access this register with 32-bit loads and stores only. todsr time-of-day seconds register 10001008 31 0 r tod seconds register w reset: undefined on por todfr tod fraction register 1000100c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r tod fraction register 0 0 0 0 0 0 0 0 w set to ones reset: undefined on por 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset:
MMC2001 programming reference motorola reference manual c-9 figure c-10 tod seconds alarm register c.3.6 tod fraction alarm register (todfar) the time-of-day fraction alarm register is a 32-bit read/write register which holds eight bits of data to be compared to the tod fraction register. the comparison is made every 1/256 of a second if the alarm function is enabled by the ae bit in the todcsr. this register is not affected by any of the reset conditions. access this register with 32-bit loads and stores only. figure c-11 tod fraction alarm register c.3.7 watchdog control register (wcr) this register contains fields that control the operation of the watchdog in different modes of operation. the write-once bits can only be written once after a reset condi- tion. subsequent attempts to write to them will not affect the data previously written. access this register with 32-bit loads and stores only. todsar time-of-day seconds alarm register 10001010 31 0 r tod seconds alarm register w reset: unaffected todfar tod fraction alarm register 10001014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r tod fraction alarm register 0 0 0 0 0 0 0 0 w reset: undefined on por 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset:
motorola programming reference MMC2001 c-10 reference manual figure c-12 watchdog control register wt watchdog time-out the six-bit wt field contains the time-out value. these bits are reloaded into the watchdog timer when it has been serviced. after reset, write wt before enabling the watchdog. the value in wt is loaded into the watchdog counter after running the ser- vice routine as well as on enabling the watchdog timer. wstp watchdog stop enable (one-time writable) 0 = watchdog not affected while in stop mode 1 = watchdog disabled while in stop mode wde watchdog enable (one-time writable) 0 = watchdog is disabled 1 = watchdog is enabled (once set, watchdog cannot be disabled) wdbg watchdog debug enable (one-time writable) 0 = watchdog not affected while in debug mode 1 = watchdog disabled while in debug mode wdze watchdog doze enable (one-time writable) 0 = watchdog not affected while in doze mode 1 = watchdog disabled while in doze mode c.3.8 watchdog service register (wsr) when enabled, the watchdog requires that a service sequence be written to the watchdog service register (wsr). this register controls the clearing of the watchdog counter to keep it from timing out and causing a reset. if this register is not written with 0x5555 followed by 0xaaaa before the selected rate expires, the watchdog sets the wdr bit in the reset source register and asserts a system reset. both writes must occur in the order listed prior to the time-out, but any number of instructions can be executed between the two writes. access this register with 32-bit loads and stores only. wcr watchdog control register 1000101c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r wt 0 0 0 0 0 0 wstp wde wdbg wdze w reset: 0 0 0 0 0 0 0 0 0 0
MMC2001 programming reference motorola reference manual c-11 figure c-13 watchdog service register c.3.9 pit control/status register (itcsr) figure c-14 pit control and status register access this register with 32-bit loads and stores only. stop stop mode control this bit controls the function of the pit in stop mode 0 = pit function is not affected while in stop mode 1 = pit function is frozen while in stop mode doze doze mode control this bit controls the function of the pit in doze mode 0 = pit function is not affected while in doze mode 1 = pit function is frozen while in doze mode dbg debug mode control this bit controls the function of the pit in debug mode 0 = pit function is not affected while in debug mode 1 = pit function is frozen while in debug mode wsr watchdog service register 10001020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 0 0 0 w watchdog service register reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 itcsr interval timer control and status register 10001024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 stop doze dbg ovw itie itif rld en w reset: 0 0 0 0 0 0 0 0
motorola programming reference MMC2001 c-12 reference manual ovw counter overwrite enable this bit controls what happens to the counter value when the modulus latch is written. 0 = modulus latch is a holding register for values to be loaded into the counter when the count expires to zero. 1 = modulus latch is transparent. all writes to the latch will also overwrite the counter contents itie pit interrupt enable this bit controls the pit interrupt function. 0 = itif is inhibited from reaching the cpu 1 = itif is allowed to request an interrupt itif pit interrupt flag this bit is the pit interrupt flag. it is cleared by writing a one to this bit or by writing to the pit data register. 0 = no pit interrupt present. 1 = pit interrupt is present. rld counter reload control this bit controls whether the value contained in the modulus latch is reloaded into the counter when the counter reaches a count of zero or whether the counter rolls over from 0 to 0xffff. 0 = counter rolls over to 0xffff. 1 = counter is reloaded from the modulus latch. en pit enable this bit controls the pit enable function. 0 = pit is disabled 1 = pit is enabled c.3.10 pit data register (itdr) on a write, the data becomes the new timer modulus. this value is retained and is used at the next and all subsequent reloads until changed by another write to itdr. this value is initialized to the maximum count of 0xffff on reset. on a read, the itdr returns the value written in the modulus latch. the only way to directly change the value of the count is to preload a modulus with the ovw bit set to one. the counter value can be read from the pit alternate data register. access this register with 32-bit loads and stores only.
MMC2001 programming reference motorola reference manual c-13 figure c-15 pit data register c.3.11 pit alternate data register (itadr) the pit alternate data register is a read-only register which provides access to the counter value. access this register with 32-bit loads and stores only. figure c-16 pit alternate data register c.4 kpp programming model itdr pit data register 10001028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r pit data w reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 itadr pit alternate data register 1000102c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r pit counter w reset: table c-4 keypad port address map address use access 10003000 keypad control register (kpcr) supervisor only 10003002 keypad status register (kpsr) supervisor only 10003004 keypad data direction register (kddr) supervisor only 10003006 keypad data register (kpdr) supervisor only 10003008 to 10003fff reserved supervisor only
motorola programming reference MMC2001 c-14 reference manual c.4.1 keypad control register (kpcr) the keypad control register (kpcr) determines which of the eight possible column strobes are to be open drain when configured as outputs and which of the eight row sense lines are considered in generating an interrupt to the core. the kpcr register is byte or halfword addressable. figure c-17 keypad control register kcox keypad column strobe open-drain enable x 0 = column strobe output x is totem-pole drive (p-channel enabled). 1 = column strobe output x is open drain (p-channel disabled). krex keypad row enable x 0 = row x is not included in keypad key press detect. 1 = row x is included in keypad key press detect. c.4.2 keypad status register (kpsr) the keypad status register (kpsr) reflects the state of the keypress detect circuit. the kpsr register is byte or halfword addressable. figure c-18 keypad status register krie key release interrupt enable 0 = no interrupt request is generated when kpkr is set 1 = an interrupt request is generated when kpkr is set kdie key depress interrupt enable 0 = no interrupt request is generated when kpkd is set 1 = an interrupt request is generated when kpkd is set krss key release synchronizer set the key release synchronizer is set by writing a logic one into this bit. reads return a value of zero. kpcr keypad control register 10003000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r kco7 kco6 kco5 kco4 kco3 kco2 kco1 kco0 kre7 kre6 kre5 kre4 kre3 kre2 kre1 kre0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 kpsr keypad status register 10003002 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 krie kdie 0 0 0 0 0 0 kpkr kpkd w krss kdsc reset: 0 0 0 0 0 0
MMC2001 programming reference motorola reference manual c-15 kdsc key depress synchronizer clear the key depress synchronizer is cleared by writing a logic one into this bit. reads return a value of zero. kpkr keypad key release 0 = no key release detected 1 = all keys have been released kpkr is cleared by writing a logic one into this bit. kpkd keypad key depress 0 = no key presses detected 1 = a key has been depressed kpkd is cleared by writing a logic one into this bit. c.4.3 keypad data direction register (kddr) the bits in the keypad data direction register (kddr) control the direction of the key- pad port pins. the kddr register is byte or halfword addressable. figure c-19 keypad data direction register kcddx keypad column x data direction 0 = colx pin is configured as input. 1 = colx pin is configured as output. krddx keypad row x data direction 0 = rowx pin is configured as input. 1 = rowx pin is configured as output. c.4.4 keypad data register (kpdr) the 16-bit keypad data register is used to access the column and row data. data writ- ten to this register is stored in an internal latch, and for each pin configured as an out- put, the stored data is driven onto the pin. a read of this register returns the value on the pin for those bits configured as inputs. otherwise, the value read is the value stored in the register. the kpdr register is byte or halfword addressable. kddr keypad data direction register 10003004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r kcdd7 kcdd6 kcdd5 kcdd4 kcdd3 kcdd2 kcdd1 kcdd0 krdd7 krdd6 krdd5 krdd4 krdd3 krdd2 krdd1 krdd0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola programming reference MMC2001 c-16 reference manual * since pins default to inputs, reset value is determined by the logic level present on the pins at reset. figure c-20 keypad data register kcdx keypad column x data bit krdx keypad row x data bit this register is not initialized by reset. valid data should be written to this register before any bits are configured as outputs. c.5 eim programming model table c-5 lists the registers in the eim. c.5.1 chip-select control registers each of the external chip selects has an enable bit as well as other control attributes. the layout of the control register is slightly different for the cs0 output, which does not support the programmable output function. for cs1Ccs3 control registers, bits two to 15 (i.e., bits other than the pa and csen bits) are undefined at reset. access these registers with 32-bit loads and stores only. kpdr keypad data register 10003006 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r kcd7 kcd6 kcd5 kcd4 kcd3 kcd2 kcd1 kcd0 krd7 krd6 krd5 krd4 krd3 krd2 krd1 krd0 w reset: * * * * * * * * * * * * * * * * table c-5 eim address map address use access 10004000 cs0 control register (cs0cr) supervisor only 10004004 cs1 control register (cs1cr) supervisor only 10004008 cs2 control register (cs2cr) supervisor only 1000400c cs3 control register (cs3cr) supervisor only 10004010 to 10004014 reserved supervisor only 10004018 eim configuration register (eimcr) supervisor only 10004020 to 10004fff reserved supervisor only
MMC2001 programming reference motorola reference manual c-17 figure c-21 cs0 control register x = undefined * pa reset value equals zero for cs3 and one for cs[1:2] figure c-22 cs1 , cs2 , cs3 control registers wsc wait-state control these four bits program the number of wait states for an access to the external device connected to the chip select. table c-6 shows the encoding of this field. when wws is cleared, setting wsc=0000 results in 1-clock transfers, wsc=0001 results in 2-clock transfers, and wsc=1111 results in 16-clock transfers. when wsc=0000, the wen and csa bits are ignored. set wsc=0000 and wws=0 for access to fast sram devices (one-clock read and write access), csa=0, wsc=0001 and wws=0 for access to normal sram (two- clock read and write access), csa=0, wsc=0001 and wws=1 for access to flash memory (two-clock read access and three-clock write access), edc, csa and wsc to the appropriate number for access to an lcd controller. cs0cr cs0 control register 10004000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r wsc wws edc csa oea wen ebc dsz sp wp 0 csen w reset: 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 cs1cr cs1 control register 10004004 cs2cr cs2 control register 10004008 cs3cr cs3 control register 1000400c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r wsc wws edc csa oea wen ebc dsz sp wp pa csen w reset: ; ; ; ; ; ; ; ; ; ; ; ; ; ;
motorola programming reference MMC2001 c-18 reference manual wws write wait state this bit is used to determine if an additional wait state is required for write cycles. this is useful for writing to flash memories that require additional data setup time. 0 = reads and writes are the same length. 1 = an additional wait state is inserted for write cycles unless wsc is set to 1111. setting wsc to 1111 results in 16-clock transfers regardless of the wws bit. read cycles are not affected. edc extra dead cycle this bit is used to determine if an idle cycle is inserted after a read cycle for back-to- back external transfers to eliminate data bus contention. this is useful for slow mem- ory and peripherals. 0 = back-to-back external transfers occur normally, i.e., no idle cycle is inserted after a read cycle. 1 = an idle cycle is inserted after a read cycle for back-to-back external transfers, unless the next cycle is a read cycle to the same cs bank. csa chip select assert this bit is used for devices that require additional address setup time and additional address/data hold times. it determines when the chip select is asserted and whether an idle cycle is inserted between back-to-back external transfers. if wsc=0000, this bit is ignored. 0 = chip select is asserted normally, i.e., as early as possible. no idle cycle is inserted between back-to-back external transfers. 1 = chip select is asserted a clock later during both read and write cycles. in addition, an idle cycle is inserted between back-to-back external transfers. table c-6 wait state control field settings number of wait states wsc[3:0] wws = 0 wws = 1 read access write access read access write access 00000001 00011112 00102223 00113334 01004445 01015556 01106667 01117778 10008889 1001 9 9 9 10 1010 10 10 10 11 1011 11 11 11 12 1100 12 12 12 13 1101 13 13 13 14 1110 14 14 14 15 1111 15 15 15 15
MMC2001 programming reference motorola reference manual c-19 oea oe assert this bit is used to determine when oe is asserted during a read cycle. if wsc=0000, this bit is ignored and oe is asserted for one half of a clock cycle only. if ebc in the corresponding register is cleared, then the eb[0:1] outputs are similarly affected. 0 = oe is asserted normally, i.e., as early as possible. 1 = oe is asserted one half of a clock cycle later during a read cycle to this chip select address space. the cycle length and write cycles are not affected. wen eb negate this bit is used to determine when eb[0:1] outputs are negated during a write cycle. this is useful to meet data hold time requirements for slow memories. if wsc=0000, this bit is ignored and eb[0:1] outputs are asserted for one half of a clock cycle only. 0 = eb[0:1] are negated normally, i.e., as late as possible. 1 = eb[0:1] are negated one half of a clock cycle earlier during a write cycle to this chip select address space. the cycle length and read cycles are not affected. ebc enable byte control this bit is used to indicate which access types should assert the enable byte outputs (eb[0:1] ). 0 = read and write accesses are both allowed to assert the eb[0:1] outputs, thus configuring them as byte enables. 1 = only write accesses are allowed to assert the eb[0:1] outputs, thus configuring them as byte write enables. the eb[0:1] outputs should be configured as byte write enables for accesses to dual x8 memories. dsz data port size this field defines the width of the device data port. sp supervisor protect this bit is used to restrict accesses to the address range defined by the correspond- ing chip select if the access is attempted in the user mode of cpu operation. 0 = user mode accesses are allowed in this chip select address range 1 = user mode accesses are prohibited. an attempted access to an address mapped by this chip select in user mode will result in a tea to the cpu and no assertion of the chip select output. table c-7 data port size field settings value meaning 8-bit port, resides on data[15:8] pins 8-bit port, resides on data[7:0] pins 16-bit port reserved
motorola programming reference MMC2001 c-20 reference manual wp write protect this bit is used to restrict writes to the address range defined by the corresponding chip select. 0 = writes are allowed in this chip select address space. 1 = writes are prohibited. an attempt to write to an address mapped by this chip select will result in a tea to the cpu and no assertion of the chip select output. pa pin assert this bit is used to control the chip select pin when it is operating as a programmable output pin (i.e. the csen bit clear). this bit is ignored if the csen bit is set. at reset, pa bit is set for cs[1:2] and cleared for cs3. 0 = brings chip select output to logic-low level 1 = brings chip select output to logic-high level csen chip select enable this bit controls the operation of the chip select pin. 0 = chip select function is disabled. an attempted access to an address mapped by this chip select will result in tea assertion to the cpu and no assertion of the chip select output. when disabled, the pin is a general-purpose output controlled by the value of the pa control bit. when csen0 is clear, cs0 is inactive. 1 = chip select is enabled and is asserted when an access address falls within the range specified in table c-8 . with the exception of cs0 , this bit is cleared by reset, disabling the chip select output pin. csen0 is set at reset to allow cs0 to select from an external boot rom if mod is driven to a logic-low level four low_refclk clock cycles before rstout negation. when the chip select is enabled, the pa control bit is ignored. c.5.2 eim configuration register the eim configuration register contains control bits that configure the eim and other internal blocks for certain operation modes. access this register with 32-bit loads and stores only. table c-8 chip-select address range addr[31:24] chip select inactive 00101101 cs0 00101111 cs1 00101110 cs2 00101100 cs3
MMC2001 programming reference motorola reference manual c-21 figure c-23 eim configuration register szen enable siz signal to uart ch1 pins this bit is used to select the function provided by the uart channel 1 pins. on reset, this bit is cleared. 0 = uart channel 0 operation. pins function as txd1, rxd1. 1 = siz function operation. pins function as siz0 and siz1 outputs independent of function or direction programmed in uart channel 1 control registers. psten enable pstat signals to uart ch0 pins this bit is used to select the function provided by the uart channel 0 pins. on reset, this bit is cleared. 0 = uart channel 0 operation. pins function as txd0, rxd0, cts0 , and rts0 . 1 = pstat function operation. pins function as pstat outputs independent of function or direction programmed in uart channel 0 control registers. spram internal ram supervisor protect this bit is used to restrict accesses to the internal ram space if the access is attempted in the user mode of cpu operation. on reset, this bit is set. 0 = user mode accesses are allowed to the internal ram. 1 = user mode accesses are prohibited. an attempted access to the internal ram in user mode will result in tea assertion to the cpu. sprom internal rom supervisor protect this bit is used to restrict accesses to the internal rom space if the access is attempted in the user mode of cpu operation. on reset, this bit is set. 0 = user mode accesses are allowed to the internal rom. 1 = user mode accesses are prohibited. an attempted access to the internal rom in user mode will result in a tea to the cpu. hdb high data bus this bit is used to determine which byte lanes of the internal data bus are driven onto the external data bus when show cycles are enabled. this bit is ignored if shen is cleared. 0 = lower internal data bus bits data[15:0] are driven externally. 1 = upper internal data bus bits data[31:16] are driven externally. eimcr eim configuration register 10004018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 szen pst en sp ram sp rom hdb shen w reset: 1 1 0 0 0
motorola programming reference MMC2001 c-22 reference manual shen show cycle enable these two bits are used to determine what the eim does with the external bus during internal transfers (i.e., an access to the internal rom, ram or peripherals). when show cycles are enabled, the internal address and data bus are driven externally. on reset, show cycles are disabled. c.6 pwm module this section describes the registers and control bits in the pwm module. all registers reset to 0x0000. these registers must be accessed with halfword accesses. accesses other than half- word in size result in undefined activity. table c-9 show cycle enable field settings value meaning show cycles disabled. the external address bus is driven with the last valid external address, and the data bus values are held by bus keepers. show cycles enabled. internal termination to the cpu during idle cycles caused by edc or csa being set follows normal operation. this means that internal transfers that occur during edc/csa idle cycles will not be visible externally. show cycles enabled. internal termination to the cpu during idle cycles caused by edc or csa being set is delayed by one clock. this ensures that all internal transfers can be externally monitored, at the expense of performance. reserved table c-10 pwm address map address use access 10005000 pwm0 control register (pwmcr0) supervisor only 10005002 pwm0 period register (pwmpr0) supervisor only 10005004 pwm0 width register (pwmwr0) supervisor only 10005006 pwm0 counter register (pwmctr0) supervisor only 10005008 pwm1 control register (pwmcr1) supervisor only 1000500a pwm1 period register (pwmpr1) supervisor only 1000500c pwm1 width register (pwmwr1) supervisor only 1000500e pwm1 counter register (pwmctr1) supervisor only 10005010 pwm2 control register (pwmcr2) supervisor only 10005012 pwm2 period register (pwmpr2) supervisor only 10005014 pwm2 width register (pwmwr2) supervisor only 10005016 pwm2 counter register (pwmctr2) supervisor only 10005018 pwm3 control register (pwmcr3) supervisor only 1000501a pwm3 period register (pwmpr3) supervisor only 1000501c pwm3 width register (pwmwr3) supervisor only 1000501e pwm3 counter register (pwmctr3) supervisor only 10005020 pwm4 control register (pwmcr4) supervisor only 10005022 pwm4 period register (pwmpr4) supervisor only
MMC2001 programming reference motorola reference manual c-23 c.6.1 pwm control register the pwm control register (pwmcr) controls the overall operation of the pwm chan- nel. the status of the channel pin is also accessible. figure c-24 pwm control registers doze doze mode when the cpu executes a doze instruction and the system is placed in doze mode, the doze bit affects operation of the pwm channel. if this bit is set, the pwm chan- nel is disabled in doze mode. pwm channel operation is suspended at the end of the current period. if irq_en is set, an interrupt request is still generated following the period compare that causes suspension. this interrupt may selectively cause the cpu to exit doze mode. 0 = pwm channel is unaffected in doze mode 1 = pwm channel is disabled in doze mode at reset, this bit is cleared to zero. 10005024 pwm4 width register (pwmwr4) supervisor only 10005026 pwm4 counter register (pwmctr4) supervisor only 10005028 pwm5 control register (pwmcr5) supervisor only 1000502a pwm5 period register (pwmpr5) supervisor only 1000502c pwm5 width register (pwmwr5) supervisor only 1000502e pwm5 counter register (pwmctr5) supervisor only 10005030 to 10005fff reserved supervisor only 10006000 to 10006fff not used (access causes transfer error) not applicable pwmcr0 pwm0 control register 10005000 pwmcr1 pwm1 control register 10005008 pwmcr2 pwm2 control register 10005010 pwmcr3 pwm3 control register 10005018 pwmcr4 pwm4 control register 10005020 pwmcr5 pwm5 control register 10005028 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 doze pwm irq irq en load data dir pol mode count en clksel w reset: 0 0 0 0 0 0 0 0 0 0 0 table c-10 pwm address map (continued) address use access
motorola programming reference MMC2001 c-24 reference manual pwm irq pwm interrupt request this bit indicates that an interrupt was posted by a period compare. this bit can be set by the user to post a pwm interrupt immediately for debugging purposes. this bit is cleared automatically after it is read while set. if irq en is cleared, this bit remains cleared. 0 = no interrupt posted 1 = pwm period rolled over irq en interrupt request enable this bit controls pwm interrupt generation. while this bit is low, the interrupt is dis- abled. 0 = pwm interrupt disabled 1 = pwm interrupt enabled load load pwmpr and pwmwr setting this bit forces a new period. the period and width registers are loaded into the comparator latches and the counter is reset. this bit is cleared automatically after the load has been performed. the actual load occurs some time after the cpu writes this bit, as the load occurs on the next rising pclk edge following internal synchroniza- tion. forcing a load of the comparator latches and counter in this manner must be done with caution to avoid unexpected pin behavior. data pwm data this bit indicates or controls the current state of the pwm pin. when the pin is config- ured as a general-purpose output, the logical value written to this bit is used to drive the pin. when the pin is configured as a general-purpose input, the pin value is reflected by this bit. when the pin is configured in pwm mode, the bit reflects the value being driven on the pin by the pwm logic. dir direction this bit controls the direction of the pin when used as a gpio pin. this bit has no affect when mode indicates pwm mode. 0 = pin is an input pin 1 = pin is an output pin pol polarity this bit controls the polarity of the pin when used as a pwm output pin. normally, the output pin is set high at period boundaries and goes low when a width compare event occurs. this bit is ignored if the pin is being used as a gpio pin. 0 = normal pwm polarity 1 = inverted pwm polarity mode pwm mode this bit selects whether the pwm pin is used for gpio or for the pwm function. 0 = general-purpose i/o mode 1 = pwm mode
MMC2001 programming reference motorola reference manual c-25 count en counter enable this bit enables or disables the pwm counter. the counter is actually enabled or dis- abled some time after the cpu writes this bit, as the enable occurs on the next rising pclk edge following internal synchronization. disabling the counter once it has been running occurs following the next period match. 0 = pwm disabled. while disabled, the counter is in low-power mode and does not count. the following events occur: when the output pin is configured to operate in pwm mode (mode =1), the output pin is forced to the setting of the pol bit. the counter is reset to 00 and frozen. the contents of the width and period registers are loaded into the compara- tors. the comparators are disabled. if the counter has been running, and the actual disable occurs at the occur- rence of a period match, an interrupt request may still be generated, even though the counter is being disabled. to avoid this, write the interrupt enable control bit (irq_en) to zero when disabling the counter. 1 = pwm is enabled and begins a new period. the following events occur: the output pin changes state to start a new period (if width != 0 and period != 0 and width < period). the counter is released and begins counting the comparators are enabled the pwm irq bit is set, indicating the start of a new period if irq en is set. clk sel clock select these bits select the output of the divider chain. c.6.2 pwm period register the pwm period register (pwmpr) controls the period of the pwm by defining the number of pclks in the period. when the counter value matches the value in this register, an interrupt is posted and the counter is reset to start another period. table c-11 clock select field values value divide by 000 4 001 8 010 16 011 64 100 256 101 2048 110 16384 111 65536
motorola programming reference MMC2001 c-26 reference manual figure c-25 pwm period registers period pulse period this value causes the counter to be reset. there is one special case. when period = 0, the output is never set high (0% duty cycle). in this case, the comparator is loaded and the counter is reset on every pclk. in addition, if enabled, an interrupt request is generated on every pclk. c.6.3 pwm width register the pwm width register (pwmwr) defines the pulse width in pclks. when the counter matches the value in this register, the output is reset for the duration of the period. note that if the value in this register is not less than the period register, the output will never be reset, resulting in a 100% duty cycle. figure c-26 pwm width registers width pulse width when the counter reaches the value in this register, the output is reset. pwmpr0 pwm0 period register 10005002 pwmpr1 pwm1 period register 1000500a pwmpr2 pwm2 period register 10005012 pwmpr3 pwm3 period register 1000501a pwmpr4 pwm4 period register 10005022 pwmpr5 pwm5 period register 1000502a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 period w reset: 0 0 0 0 0 0 0 0 0 0 pwmwr0 pwm0 width register 10005004 pwmwr1 pwm1 width register 1000500c pwmwr2 pwm2 width register 10005014 pwmwr3 pwm3 width register 1000501c pwmwr4 pwm4 width register 10005024 pwmwr5 pwm5 width register 1000502c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 width w reset: 0 0 0 0 0 0 0 0 0 0
MMC2001 programming reference motorola reference manual c-27 c.6.4 pwm counter register the read-only pwm counter register (pwmcr) holds the current count value. it can be read at any time without disturbing the counter. figure c-27 pwm count registers count count value this is the current count value. c.7 edge port programming model access the edge port registers with halfword accesses. c.7.1 edge port pin assignment register (eppar) the 16-bit read/write edge port pin assignment register (eppar) configures each of the interrupt pins as either level-sensitive or edge-sensitive. rising, falling, or both edges can be selected as the active edge. requests are always generated out of this block but may be masked within the interrupt controller module. the functionality of this register is independent of the programmed pin direction. pwmcr0 pwm0 counter register 10005006 pwmcr1 pwm1 counter register 1000500e pwmcr2 pwm2 counter register 10005016 pwmcr3 pwm3 counter register 1000501e pwmcr4 pwm4 counter register 10005026 pwmcr5 pwm5 counter register 1000502e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 count w reset: 0 0 0 0 0 0 0 0 0 0 table c-12 gpio edge port address map address use access 10007000 edge port pin assignment register (eppar) supervisor only 10007002 edge port data direction register (epddr) supervisor only 10007004 edge port data register (epdr) supervisor only 10007006 edge port flag register (epfr) supervisor only 10007008 to 10007fff reserved supervisor only
motorola programming reference MMC2001 c-28 reference manual figure c-28 edge port pin assignment register eppax edge port pin assignment select field x pins configured as level-sensitive are inverted so that a logic low on the external pin represents a valid interrupt request. level-sensitive interrupt inputs are not latched. to guarantee that a level-sensitive interrupt request is acknowledged, the interrupt source must keep the signal asserted until acknowledged by software. pins configured as edge-sensitive interrupts are latched for interrupt generation pur- poses and need not remain asserted for interrupt generation. when the pin is pro- grammed to use the edge detecting circuit, its state is monitored regardless of its configuration as input or output. these bits are cleared by hardware reset. c.7.2 edge port data direction register (epddr) the 16-bit read/write edge port data direction register (epddr) controls the direction of the port pins. setting any bit in this register configures the corresponding pin as an output. clearing any bit in this register configures the corresponding pin as an input. pin direction is independent of the level/edge mode programmed. figure c-29 edge port data direction register eppar edge port pin assignment register 10007000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r eppa7 eppa6 eppa5 eppa4 eppa3 eppa2 eppa1 eppa0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table c-13 eppax field settings value meaning 00 pin intx defined as level sensitive 01 pin intx defined as rising edge detect 10 pin intx defined as falling edge detect 11 pin intx defined as both falling and rising edge detect epddr edge port data direction register 10007002 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 epdd7 epdd6 epdd5 epdd4 epdd3 epdd2 epdd1 epdd0 w reset: 0 0 0 0 0 0 0 0
MMC2001 programming reference motorola reference manual c-29 epddx edge port data direction x 0 = pin intx is an input. 1 = pin intx is an output. these bits are cleared by reset. c.7.3 edge port data register (epdr) the edge port data register (epdr) is a 16-bit register. writes to epdr are stored in an internal latch, and if any pin of the port is configured as an output, the data stored for that bit is driven onto the pin. reads of this register return the value sensed on the pins for those pins configured as inputs, or the data stored in the register for the pins configured as outputs. x = unaffected by reset figure c-30 edge port data register epd[7:0] edge port data bits 7:0 see the above description. these bits are not affected by hardware reset. c.7.4 edge port flag register (epfr) the 16-bit read/write edge port flag register (epfr) indicates whether the selected edge has been detected on the port pins. figure c-31 edge port flag register epfx edge port flag bit x 0 = selected edge for intx pin has not been detected. 1 = selected edge for intx pin has been detected. bits in this register are set when the programmed edge is detected on the corre- sponding pin. a bit remains set until cleared by writing it to a one. pin transitions do not affect this register if the pin is configured as level sensitive (epparn=00), and the corresponding flag bit(s) are cleared to zero in this case. when a pin is configured as a general-purpose output, writes to epdr which cause the selected level or edge epdr edge port data register 10007004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 epd7 epd6 epd5 epd4 epd3 epd2 epd1 epd0 w reset: x x x x x x x x epfr edge port flag register 10007006 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 epf7 epf6 epf5 epf4 epf3 epf2 epf1 epf0 w reset: 0 0 0 0 0 0 0 0
motorola programming reference MMC2001 c-30 reference manual interrupt will set the corresponding bit in epfr. the outputs of this register drive the corresponding input of the interrupt controller for those bits configured as edge detecting. these bits are cleared by hardware reset. c.8 ispi programming model these registers control the operation of the ispi and report its status. the data regis- ter exchanges data with external slave devices. after reset, all bits are cleared. access these registers with halfword accesses. accesses other than halfword in size result in undefined activity. c.8.1 ispi send/receive data register the ispi send/receive data register (spdr) contains data to be exchanged with external devices. either writing or reading this register clears any set interrupt. figure c-32 ispi data register rx data receive data this read-only register contains the data bits received from the shift register. those bits more significant than the size determined in clock count (ispi control regis- ter) return zeros when read. for example, if clock count = 0x8 (9-bit transfer), then bits 15 to 9 are forced to zeros. the value in this register is updated at the end of every transfer. tx data transmit data this write-only register contains the data bits to be transmitted to the external device. data is copied from this register to the shift register at the time that the xch bit is set. as data is shifted msb first, outgoing data is msb-justified relative to the clock count field in the ispi control register. for example, if the exchange length is ten bits (clock count = 0x9), the msb of the outgoing data is bit nine. the first bit presented to the external device is bit nine, followed by the remaining nine less signif- icant bits. table c-14 interval mode serial peripheral interface address map address use access 10008000 ispi send/receive data register (spdr) supervisor only 10008002 ispi control register (spcr) supervisor only 10008004 ispi interval control register (spicr) supervisor only 10008006 ispi status register (spsr) supervisor only 10008008 to 10008fff reserved supervisor only spdr ispi data register 10008000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rx data w tx data reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MMC2001 programming reference motorola reference manual c-31 c.8.2 ispi control register the ispi control register (spcr), along with the ispi interval control register, controls the operation of the ispi. follow this sequence when changing operating modes: 1. disable the ispi (count = 0). 2. wait for any transfer to complete (xch bit clear). 3. update to the new mode. 4. re-enable the ispi (count = newcount). figure c-33 ispi control register doze doze mode when the cpu executes a doze instruction and the system is placed in doze mode, the doze bit affects operation of the ispi. when this bit is set, the ispi is disabled in doze mode. 0 = ispi unaffected in doze mode 1 = ispi disabled in doze mode at reset, this bit is cleared to zero. spi_en ispi enable in either master mode, this bit controls the value of the spi_en pin. the sense of the spi_en pin is determined by the sns bit. in interval mode, the spi_en pin is asserted only when xch is active. the spi_en bit must be programmed to a one for any master mode transfer to occur. in slave mode, the ispi state machine uses the input value on the spi_en pin, and this register bit is ignored. further, the spi_en register bit will not reflect the value of the spi_en pin in slave mode. 0 = negated 1 = asserted sns spi_en sense the sns bit controls the sense of the spi_en pin relative to the spi_en register bit in the ispi control register. this is required because in interval mode, the state machine must assert and then negate the spi_en pin. the sns bit has an affect only when the spi_en pin is an output. if the spi_en pin is an input, then it is active low, and the sns bit has no effect. 0 = spi_en pin is active low 1 = spi_en pin is active high spcr ispi control register 10008002 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r doze spi_ en sns drv mstr irq_ en pha pol spigp baud rate clock count w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola programming reference MMC2001 c-32 reference manual drv drive type this bit controls the configuration of the spi_clk, spi_en and spi_mosi output buffers in either master mode of the ispi (mstr=1). in slave mode, this bit is ignored. 0 = outputs are totem-pole while in either master mode 1 = outputs are open-drain while in either master mode mstr master mode this bit controls the mode of the ispi. in slave mode, the spi_clk and spi_en pins are inputs; in master modes, they are outputs. 0 = ispi operates in slave mode 1 = ispi operates in either interval mode or manual mode (see ivl_en in sicr) irq_en interrupt request enable this bit enables/disables the ispi interrupt request output signal. this bit is cleared to zero on reset. 0 = interrupts disabled 1 = interrupts enabled pha phase this bit controls the phase shift of the spi_clk. 0 = normal phase 1 = shift advance to opposite phase pol polarity this bit controls the polarity of the spi_clk. 0 = normal polarity 1 = inverted polarity spigp spi_gp control this bit controls the data on the spi_gp pin. 0 = pin driven low 1 = pin driven high baud rate these bits select the baud rate of the ispi bit clock based on divisions of the system clock. the master clock for the ispi is hi_refclk. table c-15 baud rate values value divide by 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024
MMC2001 programming reference motorola reference manual c-33 clock count these bits select the length of the transfer and control the justification of data. from two to 16 bits can be transferred. a count of all zeros causes the ispi to be disabled. c.8.3 ispi interval control register the ispi interval control register (spicr) controls interval mode operation. figure c-34 ispi interval control register lpbk loopback this bit enables a loopback test feature in the ispi. when looping back, the ispi operates as if the spi_miso and spi_mosi pins are wired together and there are no other external devices connected to the ispi data input pin. whenever loopback is enabled, the data read from the ispi data register after a given transfer matches what was written to the ispi data register prior to that transfer, masked if necessary to account for the number of bits transferred. 0 = loopback disabled 1 = loopback enabled ivl_en interval mode enable this bit, when set, places the ispi in interval mode. if the mstr bit in the ispi control register is cleared, then the ispi is operating in slave mode, and this bit is ignored. 0 = ispi is not operating in interval mode 1 = ispi is operating in interval mode if mstr=1 interval count in interval mode, this register value is loaded into the ispi interval timer upon comple- tion of a transfer. each bit-clock period, the value in this counter is decremented by one. when the value in the register reaches zero, then xch is set, and a new transfer is begun. table c-16 clock count values value meaning 0000 disable ispi 0001 2-bit transfer . . . . 0111 8-bit transfer . . . . 1111 16-bit transfer spicr ispi interval control register 10008004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 lpbk ivl_ en interval count w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola programming reference MMC2001 c-34 reference manual c.8.4 ispi status register the ispi status register (spsr) contains flags indicating whether an overrun condi- tion has occurred, an interrupt has been requested, and whether a transfer is being performed. figure c-35 ispi status register ovr overrun this register bit is set by the ispi controller when a new value is loaded into the rx while the rx is holding previously received data which has not been read. this occurs when spi_en becomes inactive and the bit timer has already timed out or when the bit counter times out a second time while spi_en remains asserted. it could also be set in interval or manual master mode if the rx data register is not read between transfers. in these cases, the ovr bit may be ignored if appropriate. 0 = no overrun event has occurred 1 = an overrun event has occurred this bit is cleared by writing it to a one or by reset. irq interrupt request this register bit is cleared on either a write or a read of the ispi data register, and when set indicates that an interrupt has been requested. 0 = no interrupt has been requested 1 = an interrupt has been requested xch exchange this bit reads the value of xch, which indicates when the state machine is perform- ing a transfer. in manual mode, xch is set by writing the ispi data register. in interval mode, xch is set automatically by the interval timer. in slave mode, xch is set when pin spi_en is asserted and is negated briefly once the counters determine the com- pletion of a transfer. it is then reasserted if spi_en is still asserted. in all modes, xch is reset upon completion of a transfer. 0 = spi is idle or interval timer is operating 1 = initiate exchange or exchange in progress c.9 uart programming model all uart registers may be accessed either as a halfword or as a byte. the rx and tx data registers may also be accessed as 32-bit words. for these registers the upper 16 bits are forced to zeros. spsr ispi status register 10008006 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ovr irq xch 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MMC2001 programming reference motorola reference manual c-35 table c-17 uart module address map address use access uart0 10009000 uart0 receive register (u0rx) supervisor only 10009002 not used supervisor only 10009004 to 1000903e u0rx echoes on word boundaries supervisor only 10009040 uart0 transmit register (u0tx) supervisor only 10009042 reserved supervisor only 10009044 to 1000907e u0tx echoes on word boundaries supervisor only 10009080 uart0 control register 1 (u0cr1) supervisor only 10009082 uart0 control register 2 (u0cr2) supervisor only 10009084 uart0 baud rate generator register (u0brgr) supervisor only 10009086 uart0 status register (u0sr) supervisor only 10009088 uart0 test register (u0tsr) supervisor only 1000908a uart0 port control register (u0pcr) supervisor only 1000908c uart0 data direction register (u0ddr) supervisor only 1000908e uart0 port data register (u0pdr) supervisor only 10009090 to 10009fff reserved supervisor only uart1 1000a000 uart1 receive register (u1rx) supervisor only 1000a002 not used supervisor only 1000a004 to 1000a03e u1rx echoes on word boundaries supervisor only 1000a040 uart1 transmit register (u1tx) supervisor only 1000a042 reserved supervisor only 1000a044 to 1000a07e u1tx echoes on word boundaries supervisor only 1000a080 uart1 control register 1 (u1cr1) supervisor only 1000a082 uart1 control register 2 (u1cr2) supervisor only 1000a084 uart1 baud rate generator register (u1brgr) supervisor only 1000a086 uart1 status register (u1sr) supervisor only 1000a088 uart1 test register (u1tsr) supervisor only 1000a08a uart1 port control register (u1pcr) supervisor only 1000a08c uart1 data direction register (u1ddr) supervisor only 1000a08e uart1 port data register (u1pdr) supervisor only 1000a088 to 1000afff reserved supervisor only 1000b000 to 1fffffff not used (access causes transfer error) not applicable
motorola programming reference MMC2001 c-36 reference manual c.9.1 uart receive register (urx) this read-only register contains received characters and status. after reset, if the receiver is enabled (rxen = 1), the charrdy bit is zero until the first character is received, and the remainder of the register contents are undefined. the rx register is echoed to 16-word addresses in order to support unloading the fifo with the load register quadrant ( ldq ) instruction. *echoes begin at 10009004 and 1000a004 respectively. x = undefined figure c-36 uart receive register charrdy character ready this read-only bit indicates whether the character in the rx data field and associ- ated flags are valid and ready to be read by the host. 0 = character in rx data field and associated flags are invalid 1 = character in rx data field and associated flags valid and ready for reading at reset, this bit is cleared to zero. err error detect when set, this read-only bit indicates that the character present in the rx data field has an error status. the error can be an ovrrun, frmerr, brk or prerr. this bit is updated and valid for each received character. 0 = no error status detected 1 = error status detected at reset, this bit is cleared to zero. ovrrun receiver overrun when set, this read-only bit indicates that the receiver ignored data to prevent over- writing the data in the fifo. under normal circumstances, this bit should never be set. it indicates that the users software is not keeping up with the incoming data rate. this bit is updated and valid for each received character, and when set indicates that some number of characters were lost following the character for which the flag is set. 0 = no fifo overrun 1 = a fifo overrun was detected at reset, this bit is cleared to zero. frmerr frame error when set, this read-only bit indicates that the current character had a framing error (missing stop bit). the data is possibly corrupted. this bit is updated for each charac- ter read from the fifo. u0rx uart0 receive register 10009000* u1rx uart1 receive register 1000a000* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r char rdy err ovr run frm err brk pr err 0 0 rx data w reset: 0 x x x x x x x x x x x x x x x
MMC2001 programming reference motorola reference manual c-37 every attempt has been made to allow the receiver to correctly interpret data follow- ing a character marked as having a framing error. (this includes ignoring the start bit validation logic, if appropriate.) however, when the transmitted data includes two stop bits, and both stop bits are incorrect, then the second stop bit will be interpreted as the start bit of the next character. 0 = character has no framing error 1 = character has a framing error at reset, this bit is cleared to zero. brk break detect when set, this read-only bit indicates that the current character was detected as a break. the data bits are all zero and the stop bit is also zero. the frame error bit is always set when this bit is set. when odd parity is selected, parity error is set when this bit is set. this bit is valid for each character read from the fifo. 0 = character is not a break character 1 = character is a break character at reset, this bit is cleared to zero. prerr parity error when set, this read-only bit indicates that the current character was detected with a parity error. the data is possibly corrupted. this bit is updated for each character read from the fifo. while parity is disabled, this bit always reads zero. 0 = no parity error detected for data in rx data field 1 = parity error detected for data in rx data field at reset, this bit is cleared to zero. rx data received data these read-only bits are the received character. in 7-bit mode, the msb is forced to zero. in 8-bit mode, all bits are active. c.9.2 uart transmit register (utx) the uart transmit register is used by the host to write the data to be transmitted. the low byte is write-only. when this register is read, bits tx[15:8] always return zero, and tx[7:0] is not driving the bus. the tx register is echoed to 16-word addresses in order to support filling the transmit fifo with the store register quadrant ( stq ) instruction. *echoes begin at 10009044 and 1000a044 respectively. x = undefined figure c-37 uart transmit register u0tx uart0 transmit register 10009040* u1tx uart1 transmit register 1000a040* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 w tx data reset: 0 0 0 0 0 0 0 0 x x x x x x x x
motorola programming reference MMC2001 c-38 reference manual tx data transmit data these write-only bits are the parallel transmit data inputs. in 7-bit mode, d7 is ignored. in 8-bit mode, all bits are used. data is transmitted lsb first. a new charac- ter is transmitted when these bits are written. these bits must be written only while trdy is high to ensure that corrupted data is not sent. c.9.3 uart control register 1 (ucr1) uart control register 1 is a read/write register. this register enables the uart and the transmit and receive blocks. it controls the tx and rx fifo levels and enables the trdy and rrdy interrupts. figure c-38 uart control register 1 txfl transmitter fifo interrupt trigger level these bits control the operation of the interrupt generated by the transmitter. a maskable interrupt is generated whenever the data level in the tx fifo drops below the selected threshold. the bits are encoded as follows: at reset, these bits are cleared to zero. trdyen transmitter ready interrupt enable setting this bit enables an interrupt when the transmitter has one or more slots avail- able in the tx fifo. the fill level in the tx fifo at which an interrupt is generated is controlled by the txfl bits. while this bit is negated, the transmitter interrupt is dis- abled. 0 = tx interrupt disabled 1 = tx interrupt enabled at reset, this bit is cleared to zero. txen transmitter enable this bit enables or disables the transmitter. while uarten and txen bits are set, and doze bit is cleared, the transmitter is enabled. if this bit is cleared in the middle of a transmission, the uart disables the transmitter immediately and starts marking ones. u0cr1 uart0 control register 1 10009080 u1cr1 uart1 control register 1 1000a080 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r txfl trdy- en txen rxfl rrdy en rxen iren 0 rtsd en snd- brk 0 0 doze uart en w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 table c-18 txfl field settings value meaning 00 interrupt if tx fifo has a slot for one or more character 01 interrupt if tx fifo has a slot for four or more characters 10 interrupt if tx fifo has a slot for eight or more characters 11 interrupt if tx fifo has a slot for fourteen or more characters
MMC2001 programming reference motorola reference manual c-39 the transmitter fifo cannot be written when this bit is cleared. 0 = transmitter disabled 1 = transmitter enabled at reset, this bit is cleared to zero. rxfl receiver fifo interrupt trigger level these bits control the threshold at which a maskable interrupt is generated by the receiver. a maskable interrupt is generated whenever the data level in the rx fifo reaches the selected threshold. at reset, these bits are cleared to zero. rrdyen receiver ready interrupt enable setting this bit enables an interrupt when the receiver has data in the rx fifo. the fill level in the rx fifo at which an interrupt is generated is controlled by the rxfl bits. clearing this bit disables rx interrupts. 0 = rx interrupt disabled 1 = rx interrupt enabled at reset, this bit is cleared to zero. rxen receiver enable setting this bit enables the receiver. if the rxd line is already low when the receiver is enabled, the receiver does not recognize break characters, since it requires a valid one-to-zero transition before it can accept any character. 0 = receiver disabled 1 = receiver enabled at reset, this bit is cleared to zero. iren infrared interface enable this active high bit enables the infrared interface. 0 = infrared interface disabled 1 = infrared interface enabled at reset, this bit is cleared to zero. rtsd en rts delta interrupt enable this bit enables or disables rts delta interrupts. the current status of the rts pin is read in the uart status register. 0 = rts interrupt disabled 1 = rts interrupt enabled at reset, this bit is cleared to zero. table c-19 rxfl field settings value meaning 00 interrupt if rx fifo contains one or more character 01 interrupt if rx fifo contains four or more characters 10 interrupt if rx fifo contains eight or more characters 11 interrupt if rx fifo contains fourteen or more characters
motorola programming reference MMC2001 c-40 reference manual sndbrk send break this bit forces the transmitter to send a break character. the transmitter will finish sending the character in progress (if any) and then send break characters until this bit is reset. the user is responsible for ensuring that this bit is high for a sufficient period of time to generate a valid break; the transmitter samples sndbrk after every bit is transmitted. following completion of the break transmission, the uart transmits two mark bits. the user can continue to fill the fifo, and any characters remaining will be transmit- ted when the break is terminated. this bit cannot be changed until the uart en and tx en bits in the uart control register 1 (uxcr1) are set. 0 = do not send break 1 = send break (continuous zeros) at reset, this bit is cleared to zero. doze when the cpu executes a doze instruction and the system is placed in the doze mode, the doze bit affects operation of the uart. if this bit is set when the system is in the doze mode, the uart is disabled. 0 = uart unaffected while the mcu is in doze mode 1 = uart disabled while the mcu is in doze mode at reset, this bit is cleared to zero. uart en uart enable this bit enables or disables the uart. if this bit is cleared in the middle of a transmis- sion, the transmitter stops and drives the txd line to logic one. 0 = uart disabled 1 = uart enabled at reset, this bit is cleared to zero. c.9.4 uart control register 2 (ucr2) uart control register 2 is a read/write register. this register controls the overall oper- ation of the uart. it controls the clock source, number of bits per character, parity generation and checking, and behavior of the rts , cts , and dtr pins. figure c-39 uart control register 2 u0cr2 uart0 control register 2 10009082 u1cr2 uart1 control register 2 1000a082 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 irts ctsc cts 0 0 0 pren proe stpb ws 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0
MMC2001 programming reference motorola reference manual c-41 irts ignore rts setting this bit forces the rts input signal presented to the transmitter to always be asserted, effectively causing the external pin to be ignored. in this mode, the rts pin can be used as a general-purpose input. 0 = transmit only while rts pin is asserted 1 = ignore rts pin at reset, this bit is cleared to zero. ctsc cts pin control this bit controls the operation of the cts output pin. while this bit is set, the cts out- put pin is controlled by the receiver. when the rx fifo has a pending overrun, the cts output pin is negated to indicate to the far-end transmitter to stop transmitting. while the ctsc bit is negated, the cts output pin is controlled by the cts bit. on reset, since this bit is cleared to zero, the cts pin is controlled by the cts bit, which is also cleared to zero on reset. this means that on reset the cts signal is negated. 0 = cts pin controlled by the cts bit 1 = cts pin controlled by the receiver at reset, this bit is cleared to zero. cts cts bit this bit controls the cts pin while the ctsc bit is negated. while ctsc is asserted this bit has no function. 0 = cts pin is driven high (inactive) 1 = cts pin is driven low (active) at reset, this bit is cleared to zero. pren parity enable this bit enables or disables the parity generator in the transmitter and parity checker in the receiver. 0 = parity disabled 1 = parity enabled at reset, this bit is cleared to zero. proe parity odd/even this bit controls the sense of the parity generator and checker. when proe is set, odd parity is generated and expected. when proe is cleared, even parity is gener- ated and expected. this bit has no function if pren is low. 0 = even parity 1 = odd parity at reset, this bit is cleared to zero. stpb stop bits this bit controls the number of stop bits transmitted after a character. when stpb is set, two stop bits are sent. when stpb is cleared, one stop bit is sent. this bit has no effect on the receiver, which expects one or more stop bits. 0 = one stop bit transmitted 1 = two stop bits transmitted at reset, this bit is cleared to zero.
motorola programming reference MMC2001 c-42 reference manual ws word size this bit specifies a character length of eight or seven bits (not including start, stop, or parity bits). when ws is set, the transmitter and receiver are in eight-bit mode. when ws is cleared, they are in seven-bit mode. the transmitter then ignores b7, and the receiver sets b7 to zero. this bit can be changed between transmissions or recep- tions. if it is changed while a transmission or reception is in progress, however, the length of the current character being transmitted or received is unpredictable. 0 = 7-bit transmit and receive character length 1 = 8-bit transmit and receive character length at reset, this bit is cleared to zero. c.9.5 uart brg register (ubrgr) this register specifies the divide ratio of the prescaler in the uart bit clock genera- tor. figure c-40 uart brg register cd clock divider these bits determine the bit clock generator output rate. the cd field is used to pre- set a 12-bit counter that is decremented at the system clock rate. the value 0x000 produces the maximum clock rate (equal to the system clock). the value 0xfff pro- duces the minimum clock rate (divide by 4096). c.9.6 uart status register (usr) the read/write uart status register indicates the status of the rts pin, input transi- tions on the pin, and status of the transmit and receive fifos. figure c-41 uart status register u0brgr uart0 brg register 10009084 u1brgr uart1 brg register 1000a084 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 cd w reset: 0 0 0 0 0 0 0 0 0 0 0 0 u0sr uart0 status register 10009086 u1sr uart1 status register 1000a086 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r tx mpty rtss trdy 0 0 0 rrdy 0 0 0 rtsd 0 0 0 0 0 w reset: 1 0 1 0 0
MMC2001 programming reference motorola reference manual c-43 txmpty transmitter empty when set, this bit indicates that the transmit fifo and the transmit shift register are both empty. this bit is automatically cleared when a write to the tx fifo is per- formed. 0 = tx fifo or shifter are not both empty 1 = tx fifo and shifter are both empty at reset, this bit is set to one. rtss rts pin status this bit indicates the current status of the rts pin. a snapshot of the pin is taken immediately before this bit is presented to the data bus. while irts is asserted, this bit can be used as a general-purpose input. 0 = rts pin is high (inactive) 1 = rts pin is low (active) this bit follows the logic value connected to the rts pin. trdy transmitter ready interrupt flag when set, this bit indicates that the tx fifo has emptied below its target threshold and needs data. this bit is automatically cleared when the data level in the tx fifo goes beyond the set threshold level. 0 = transmitter does not need data 1 = transmitter needs data (interrupt posted) at reset, this bit is set to one. rrdy receiver ready interrupt flag when set, this bit indicates that the receive fifo data level is above the threshold level specified by the rxfl field, and a maskable interrupt is generated. refer to the rxfl bit description for setting the threshold level. in conjunction with the charrdy bit, host software can continue to read the rx fifo in an interrupt service routine until the rx fifo is empty. this bit is automatically cleared when the data level in the rx fifo goes below the set threshold level. 0 = no character ready (no interrupt posted) 1 = character(s) ready (interrupt posted) at reset, this bit is cleared to zero. rtsd rts delta when set, this bit indicates that the rts pin changed state. it generates a maskable interrupt. in stop mode, rts assertion sets this bit to wake the cpu. the current state of the rts pin is available in the rtss bit. the rtsd interrupt is cleared by writing a one to this bit. 0 = rts pin did not change state since last cleared 1 = rts pin changed state at reset, this bit is cleared to zero. c.9.7 uart test register (utsr) the uart test register is a read/write register. unimplemented bits always return zero when read. this register contains miscellaneous bits to control test features of the uart block.
motorola programming reference MMC2001 c-44 reference manual figure c-42 uart test register frc perr force parity error when set, this bit forces the transmitter to generate a parity error if parity is enabled. this bit is provided for system debugging. 0 = generate normal parity 1 = generate inverted parity (error) at reset, this bit is cleared to zero. loop loop tx and rx for test this bit controls loopback for test purposes. when this bit is high, the receiver input is internally connected to the transmitter and ignores the rxd pin. the transmitter is unaffected by this bit. this loopback operates to connect the data on the txd pin directly to the voting logic. if infrared mode is enabled (ir_en is active), the effect of activating this bit is to put an ir-formatted bit stream into the voting logic, which will yield odd results. do not use this loopback if ir_en is active. 0 = normal receiver operation 1 = internal connect transmitter output to receiver input at reset, this bit is cleared to zero. loop ir loop tx and rx for ir test this bit controls a loopback from transmitter to receiver in the infrared interface. 0 = no ir loop 1 = connect ir transmit to ir receiver at reset, this bit is cleared to zero. c.9.8 uart port control register (upcr) the read/write uart port control register controls the functionality of uart gpio pins. figure c-43 uart port control register u0tsr uart0 test register 10009088 u1tsr uart1 test register 1000a088 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 frc perr loop 0 loop ir 0 000000000 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u0pcr uart0 port control register 1000908a u1pcr uart1 port control register 1000a08a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 00000 pc3 pc2 pc1 pc0 w reset: 0 0 0 0
MMC2001 programming reference motorola reference manual c-45 pcx port control bit x 0 = corresponding pin is configured as gpio pin 1 = corresponding pin is configured as uart pin at reset, these bits are cleared to zero. c.9.9 uart data direction register (uddr) this register controls the direction of uart gpio pins. figure c-44 uart data direction register pdcx port direction control bit x 0 = corresponding gpio pin is configured as input 1 = corresponding gpio pin is configured as output at reset, these bits are cleared to zero. c.9.10 uart port data register (updr) the uart port data register is used to read or write data to or from uart gpio pins. x = undefined figure c-45 uart port data register pdx port data bit x these bits are used to read or write data from/to the corresponding port pins if they are configured as gpio (by pc[3:0] bits in upcr). if a port pin x is configured as a gpio input, then the corresponding pdx bit will reflect the value present on this pin. if a port pin x is configured as a gpio output, then the value written into the corre- sponding pdx bit will be reflected on the pin. note that since the cts and rts pins are not present for uart1, the corresponding port control register bits should be configured in a manner which provides determinis- tic data when the port data register is read. one method for doing this is to configure the missing pins as general-purpose outputs. u0ddr uart0 data direction register 1000908c u1ddr uart1 data direction register 1000a08c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 00000 pdc3 pdc2 pdc1 pdc0 w reset: 0 0 0 0 u0pdr uart0 port data register 1000908e u1pdr uart1 port data register 1000a08e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 00000pd3 pd2 pd1 pd0 w reset: x x x x
motorola programming reference MMC2001 c-46 reference manual c.10 once registers c.10.1 once command register (ocmr) the once command register (ocmr) is an 8-bit shift register that receives its serial data from the tdi pin. this register corresponds to the jtag ir, and is loaded when the update-ir tap controller state is entered. figure c-46 once command register r/w read/write command the r/w bit specifies the direction of data transfer. 0 = write the data associated with the command into the register specified by the rs field. 1 = read the data contained in the register specified by the rs field. go go command if the go bit is set, the chip executes the instruction that resides in the ir register in the cpuscr. to execute the instruction, the processor leaves debug mode, exe- cutes the instruction, and if the ex bit is cleared, returns to debug mode immediately after executing the instruction. the processor resumes normal operation if the ex bit is set. the go command is executed only if the operation is a read/write to either cpuscr or no register selected. otherwise, the go bit is ignored. the processor leaves debug mode after the tap controller update-dr state is entered. 0 = inactive (no action taken) 1 = execute instruction in ir ex exit command if the ex bit is set, the processor leaves debug mode and resumes normal operation until another debug request is generated. the exit command is executed only if the go command is issued, and the operation is a read/write to cpuscr or read/write to no register selected. otherwise the ex bit is ignored. the processor exits debug mode after the tap controller update-dr state is entered. 0 = remain in debug mode 1 = leave debug mode rs register select the register select bits define the source or destination register for the read or write operation, respectively. table c-20 indicates the once register addresses. 2&052 2q&(&rppdqg5hjlvwhu %,7%,7 5: *2 (; 56
MMC2001 programming reference motorola reference manual c-47 c.10.2 once control register (ocr) the once control register (ocr) is a 32-bit register used to select the events that put the chip in debug mode and to enable or disable sections of the once logic. the control bits are read/write. figure c-47 once control register table c-20 once register addressing rs register selected 00000 reserved 00001 reserved 00010 reserved 00011 trace counter (otc) 00100 memory breakpoint counter a (mbca) 00101 memory breakpoint counter b (mbcb) 00110 program counter fifo and increment counter 00111 breakpoint address base register a (baba) 01000 breakpoint address base register b (babb) 01001 breakpoint address mask register a (bama) 01010 breakpoint address mask register b (bamb) 01011 cpu scan register (cpuscr) 01100 no register selected (bypass) 01101 once control register (ocr) 01110 once status register (osr) 01111 reserved (factory test control register do not access) 10000 reserved (mem_bist, do not access) 10001 C 10110 reserved (bypass, do not access) 10111 reserved (lsrl, do not access) 11000 C 11110 reserved (bypass, do not access) 11111 bypass ocr once control register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sqc w reset: 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r dr idre tme frzc rcb bcb rca bca w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola programming reference MMC2001 c-48 reference manual sqc sequential control the sqc field allows memory breakpoint b and trace occurrences to be suspended until a qualifying event occurs. this field is cleared on test logic reset. dr cpu debug request control this control bit is used to request the cpu to enter debug mode unconditionally. the cpu indicates that debug mode has been entered via the pm bits in the once status register. once the cpu enters debug mode, it returns there even with a write to the ocmr with go and ex set until the dr bit is cleared. this bit is cleared on test logic reset. idre internal debug request enable this control bit is used to enable internally generated debug requests. the internal debug request input to the once control logic (idr ) may not be used in all implemen- tations. in some implementations, the idr control input may be connected and used as an additional hardware debug request. this bit is cleared on test logic reset. 0 = disable idr input operation 1 = enable idr input operation tme trace mode enable the tme control bit enables the once trace mode operation. this bit is cleared on test logic reset. trace operation is also affected by the sqc field described above. 0 = disable trace operation 1 = enable trace operation frzc freeze control this control bit is used in conjunction with memory breakpoint b registers to select between asserting a breakpoint condition when a memory breakpoint b occurs, or freezing the pc fifo from further updates when memory breakpoint b occurs while allowing the cpu to continue execution. the pc fifo remains frozen until the frzo bit in the osr is cleared. table c-21 sequential control field definition sqc[1:0] meaning disable sequential control operation. memory breakpoints and trace operation are unaf- fected by this field. suspend normal trace counter operation until a breakpoint condition occurs for memory breakpoint b. when this mode is selected, memory breakpoint b occurrences no longer cause a breakpoint request to be generated. instead, trace counter comparisons are sus- pended until the first memory breakpoint b occurrence. after the first memory breakpoint b occurrence, trace counter control is released to perform normally (assuming tme is set). this allows a sequence of breakpoint conditions to be specified prior to trace count- ing. qualify memory breakpoint b matches with a breakpoint occurrence for memory break- point a. when this bit is set, memory breakpoint a occurrences no longer cause a break- point request to be generated. instead, memory breakpoint b comparisons are suspended until the first memory breakpoint a occurrence. after the first memory break- point a occurrence, memory breakpoint b is enabled to perform normally. this allows a sequence of breakpoint conditions to be specified. combine the qualifications specified by the 01 and 10 encodings of this field. in this mode, no breakpoint requests are generated, and trace count operation is enabled (when tme is set) once a memory breakpoint b occurrence follows a memory breakpoint a occurrence.
MMC2001 programming reference motorola reference manual c-49 0 = memory breakpoint b occurrence causes assertion of a breakpoint condition 1 = memory breakpoint b occurrence causes a freeze of pc fifo from further updates and no breakpoint assertion rcb, rca memory breakpoint b, a range control these control bits condition enabled memory breakpoints. they condition whether memory breakpoint matches will occur when a memory address falls either within the range defined by memory base address and mask, or outside the range. 0 = condition breakpoint on access within range 1 = condition breakpoint on access outside of range bcb, bca memory breakpoint b, a control these control bits enable memory breakpoints and qualify the access attributes to select whether the breakpoint match will be recognized for read, write, or instruction fetch (program space) accesses. these bits are cleared on test logic reset. see table c-22 for the definition of the bca and bcb fields. table c-22 memory breakpoint control field definition bc4 bc3 bc2 bc1 bc0 description 00000breakpoint disabled 00001qualify match with any access 00010qualify match with any instruction access 00011qualify match with any data access 00100qualify match with any change of flow instruction access 00101qualify match with any data write 00110qualify match with any data read 00111reserved 01xxxreserved 10000reserved 10001qualify match with any user access 10010qualify match with any user instruction access 10011qualify match with any user data access 10100qualify match with any user change of flow access 10101qualify match with any user data write 10110qualify match with any user data read 10111reserved 11000reserved 11001qualify match with any supervisor access 11010qualify match with any supervisor instruction access 11011qualify match with any supervisor data access 11100qualify match with any supervisor change of flow access 11101qualify match with any supervisor data write 11110qualify match with any supervisor data read 11111reserved
motorola programming reference MMC2001 c-50 reference manual c.10.3 once status register (osr) the once status register (osr) is a 16-bit register used to indicate the reason(s) that debug mode was entered and the current operating mode of the cpu. these sta- tus bits are read only. figure c-48 once status register hdro hardware debug request occurrence this read-only status bit is set when the processor enters debug mode as a result of a hardware debug request from the idr signal or the de pin. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. dro debug request occurrence this read-only status bit is set when the processor enters debug mode and the debug request (dr) control bit in the once control register is set. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. mbo memory breakpoint occurrence this read-only status bit is set when a memory breakpoint request has been issued to the cpu via the brkrq input and the cpu enters debug mode. in some situations involving breakpoint requests on instruction prefetches, the cpu may discard the request along with the prefetch. in this case, this bit may become set due to the cpu entering debug mode for another reason. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. swo software debug occurrence this read-only status bit is set when the processor enters debug mode of operation as a result of the execution of the bkpt instruction. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. to trace count occurrence this read-only status bit is set when the trace counter reaches zero with the trace mode enabled and the cpu enters debug mode. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. frzo fifo freeze occurrence this read-only status bit is set when a fifo freeze occurs. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. sqb sequential breakpoint b arm occurrence this read-only status bit is set when sequential operation is enabled and a memory breakpoint b event has occurred to enable trace counter operation. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. osr once status register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 hdro dro mbo swo to frzo sqb sqa pm w reset: 0 0 0 0 0 0 0 0 0 0
MMC2001 programming reference motorola reference manual c-51 sqa sequential breakpoint a arm occurrence this read-only status bit is set when sequential operation is enabled and a memory breakpoint a event has occurred to enable memory breakpoint b operation. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. pm processor mode these status bits indicate the processor operating mode. they allow coordination of the once controller with the cpu to synchronize the two. c.10.4 memory address latch (mal) the memory address latch (mal) is a 32-bit register that latches the address bus on every access. c.10.5 breakpoint address base registers (baba, babb) the 32-bit breakpoint address base registers (baba, babb) store memory break- point base addresses. baba and babb can be read or written through the once serial interface. before enabling breakpoints, the external command controller should load these registers. c.10.6 breakpoint address mask registers (bama, bamb) the 32-bit breakpoint address mask registers (bama, bamb) store memory break- point base address masks. bama and bamb can be read or written through the once serial interface. before enabling breakpoints, the external command controller should load these registers. c.10.7 breakpoint address comparators each breakpoint address comparator compares the current memory address (stored in mal) with the contents of the base, as appropriately masked by the bamx. when a match occurs, the comparator signals the breakpoint logic. c.10.8 memory breakpoint counters (mbca, mbcb) the 16-bit memory breakpoint counter x (mbcx) register is loaded with a value equal to the number of times, minus one, that a memory access event can occur before a memory breakpoint is declared. c.10.9 program counter register (pc) the program counter register (pc) is a 32-bit latch that stores the value of the pro- gram counter that was present when the chip entered debug mode. table c-23 processor mode field definition pm[1:0] meaning 00 processor in normal mode 01 processor in stop, doze, or wait mode 10 processor in debug mode 11 reserved
motorola programming reference MMC2001 c-52 reference manual c.10.10 instruction register (ir) the instruction register (ir) provides a mechanism for controlling the debug session by forcing in selected instructions and then causing them to be executed in a con- trolled manner by the debug control block. c.10.11 control state register (ctl) the control state register (ctl) is used to set control values when debug mode is exited. on scan-in, this register is used to control specific aspects of the cpu. certain bits reflect internal processor status and should be restored to their original values. the ctl is a 16-bit latch that stores the value of certain internal cpu state variables before debug mode is entered. this register is affected by the operations performed during the debug session and should be restored by the external command controller when returning to normal mode. in addition to saved internal state variables, the bits are used by emulation firmware to control the debug process. set reserved bits to ones. figure c-49 control state register ffy feed forward y operand this control bit is used to force the content of the wbbr to be used as the y operand value of the first instruction to be executed following an update of the cpuscr. this gives the debug firmware the capability of updating processor registers by initializing the wbbr with the desired value, setting the ffy bit, and executing a mov instruc- tion to the desired register. fdb force psr debug mode a logical or of this control bit with the psr(db) bit determines whether the proces- sor is operating in debug enable mode or not. the processor can be placed in debug enable mode by setting this bit regardless of the state of the psr(db) bit. in debug enable mode, execution of the bkpt instruction as well as recognition of the brkrq input cause the processor to enter debug mode, as if the dbgrq input had been asserted. sz prefetch size this control field is used to drive the cpu siz[1:0] outputs on the first instruction prefetch caused by issuing a once command with the go bit set and not ignored. it should be set to indicate a 16-bit size, i.e., 0b10. this field should be restored to its original value after a debug session is completed, i.e., when a once command is issued with the go and ex bits set and not ignored. ctl control state register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r reserved ffy fdb sz tc reserved w reset: 0 0 0 0 0 0 0
MMC2001 programming reference motorola reference manual c-53 tc prefetch transfer code this control field is used to drive the cpu tc[2:0] outputs on the first instruction prefetch caused by issuing a once command with the go bit set and not ignored. it should typically be set to indicate a supervisor instruction access, i.e., 0b110. this field should be restored to its original value after a debug session is completed, i.e., when a once command is issued with the go and ex bits set and not ignored. c.10.12 write-back bus register (wbbr) the write-back bus register (wbbr) is used as a means of passing operand informa- tion between the cpu and the external command controller. to update a processor resource, this register is initialized with a data value to be writ- ten, and a mov instruction is executed which uses this value as a write-back data value. the ffy bit in the control state register forces the value of the wbbr to be substituted for the normal source value of a mov instruction, thus allowing updates to processor registers to be performed. c.10.13 processor status register (psr) the once processor status register (psr) is a 32-bit latch used to read or write the m?core processor status register. whenever the external command controller needs to save or modify the contents of the m?core processor status register, this register is used. this register is affected by the operations performed in debug mode and must be restored by the external command controller when returning to normal mode. c.10.14 reserved test control registers (reserved, mem_bist, ftcr, lsrl) these registers are reserved for factory testing. warning to prevent damage to the device or system, do not access these registers during normal operation.
motorola programming reference MMC2001 c-54 reference manual
MMC2001 motorola reference manual i-1 CaC ac electrical specifications a-2 addr (address bus) signals 4-4, 7-1 address bus 4-4, 7-1 ae bit 9-5, c-7 af bit 2-4 aie bit 9-5, 9-6, c-7 aif bit 9-5, 9-6, c-7 alarm enable bit 9-5, c-7 alarm interrupt enable bit 9-5, 9-6, c-7 alarm interrupt flag 9-5, 9-6, c-7 alternate file 2-3 alternate file bit 2-4 CbC baba 16-14, c-51 babb 16-14, c-51 baca 16-14, c-51 bacb 16-14, c-51 bama 16-14, c-51 bamb 16-14, c-51 baud rate field 12-7, c-32 bca bit 16-10, c-49 bcb bit 16-10, c-49 big-endian byte ordering 2-5 bit clock generator 11-4 bit time 11-4 boot mode 4-4, 7-2, 7-6 break detect bit 11-8, c-37 break frame 11-3, 11-4 breakpoint address base registers 16-14, c-51 address comparators 16-14, c-51 address mask registers 16-14, c-51 logic 16-12 brk bit 11-8, c-37 brkrq signal 16-5 bus sizing 7-4 bus watchdog 7-6 CcC c bit 2-3 cd bit 11-13, c-42 charrdy bit 11-7, c-36 chip select 4-4, 7-2 assert bit 7-9, c-18 control registers 7-7, c-16 enable bit 7-11, c-20 ckoe bit 8-7, 9-4, c-6 ckos bit 9-3, c-6 clear to send 4-7, 11-2 clk sel field 15-6, c-25 clkin signal 4-5 clkout enable bit 8-7, 9-4, c-6 clkout signal 4-5, 8-7 clkout source bit 9-3, c-6 clksrc bit 11-13 clock divider bit 11-13, c-42 input 4-5 input specifications a-2 module 8-1 block diagram 8-3 output 4-5, 8-7 select field 15-6, c-25 source 8-1 source bit 11-13 clock count field 12-7, c-33 column strobes 4-7 condition code/carry bit 2-3 control registers 2-3 control state register 16-18, c-52 count en bit 15-5, c-25 count field 15-7, c-27 counter enable bit 15-5, c-25 counter overwrite enable bit 9-14, c-12 counter reload control bit 9-12, 9-13, 9-15, c-12 cpu breakpoint request 16-5 debug acknowledge 16-5 debug request 16-5 debug request control bit 16-9, c-48 status signals 16-5 crystal oscillator 4-5 cs signals 4-4, 7-2 csa bit 7-9, c-18 csen bit 7-11, c-20 csxcr 7-7, c-16 ctl 16-18, c-52 cts bit 11-12, c-41 cts pin control bit 11-12, c-41 cts signal 11-2 cts0 4-7 ctsc bit 11-12, c-41 CdC data (data bus) signals 4-4, 7-2 index
motorola MMC2001 i-2 reference manual data bit 15-5, c-24 data bus 4-4, 7-2 data organization in memory 2-5 in registers 2-5 data port size bit 7-10, c-19 dbg bit 9-14, c-11 dbgack signal 16-5 dbgrq signal 16-5 dc electrical specifications a-1 de signal 4-6, 16-4 debug event 4-6, 16-4 mode entering 16-16 isp 12-11 select 16-3 uart 11-24 mode control bit 9-14, c-11 request occurrence bit 16-11, c-50 serial clock 16-3 serial input 16-3 serial output 16-3 debug signal 16-6 dir bit 15-5, c-24 direction bit 15-5, c-24 doze bit ispi 12-6, c-31 pit 9-14, c-11 pwm 15-4, c-23 uart 11-11, c-40 doze mode 8-4 dr bit 16-9, c-48 drive type bit 12-6, c-32 dro bit 16-11, c-50 drv bit 12-6, c-32 dsz bit 7-10, c-19 CeC eb negate bit 7-10, c-19 eb signals 4-4, 7-2 ebc bit 7-10, c-19 ebro bit 16-11, c-50 edc bit 7-9, c-18 edge port 13-1 block diagram 13-1 data direction register 13-3, c-28 data register 13-3, c-29 flag register 13-4, c-29 pin assignment register 13-2, c-27 programming model 13-2 signals 13-1 edge-triggered interrupts 13-2, c-27 ef flags 10-4, c-3 eim 7-1 bus sizing 7-4 configuration register 7-11, c-20 programming model 7-7 signals 7-1 timing specifications a-4 eimcr 7-11, c-20 electrical characteristics a-1 en bit 9-15, c-12 en flags 10-3, c-3 enable byte control bit 7-10, c-19 bytes 4-4, 7-2 fast interrupt flags 10-4, c-3 normal interrupt flags 10-3, c-3 epddr 13-3, c-28 epdr 13-3, c-29 epfr 13-4, c-29 eppar 13-2, c-27 epsr 2-3 err bit 11-7, c-36 error detect bit 11-7, c-36 ex bit 16-7, c-46 exceptions cycles 2-14 processing 2-3 shadow registers 2-4 exchange flag 12-9, c-34 exit command bit 16-7, c-46 exosc pin 4-5 external breakpoint request occurrence bit 16-11, c-50 external bus timing diagrams 7-13 external interface module. see eim external interrupts 4-6, 13-1 timing specifications a-3 extra dead cycle bit 7-9, c-18 CfC factory test mode 4-6 fast interrupt enable register 10-3, c-3 pending flags 10-5, c-5 pending register 10-5, c-4 fdb bit 16-19, c-52 feed forward y operand bit 16-19, c-52 ffy bit 16-19, c-52 fier 10-3, c-3 fifo buffer 16-20 fifo freeze occurrence bit 16-11, c-50 fipnd 10-5, c-4 force parity error bit 11-15, c-44 force psr debug enable mode bit 16-19 force psr debug mode bit c-52 fp flags 10-5, c-5 fpsr 2-3 frame 11-4 frame error bit 11-8, c-36 framing error 11-5 frc perr bit 11-15, c-44 freeze control bit 16-10, c-48 frmerr bit 11-8, c-36 frzc bit 16-10, c-48 frzo bit 16-11, c-50
MMC2001 motorola reference manual i-3 CgC general-purpose i/o 13-1 general-purpose registers 2-3 glitch suppression, kpp 14-7 gnd pin 4-9 go bit 16-7, c-46 gpio 13-1 ground 4-9 ChC hardware debug request occurrence bit 16-11, c-50 hdb bit 7-7, 7-12, c-21 hdro bit 16-11, c-50 hi_refclk 8-1 high data bus bit 7-7, 7-12, c-21 CiC idr signal 16-5 idre bit 16-9, c-48 ignore rts bit 11-2, 11-12, c-41 in bits 10-3, c-2 infrared interface 11-4 infrared interface enable bit 11-11, c-39 instruction address fifo buffer 16-20 register 16-18, c-52 timing 2-2 int signals 4-6 internal debug request enable bit 16-9, c-48 debug request input 16-5 ram supervisor protect bit 7-12, c-21 rom disable 4-4 supervisor protect bit 7-12, c-21 rom disable 7-2 interrupt controller 10-1 in low-power modes 8-5 programming model 10-2 request enable bit 15-4, c-24 request flag 12-9, c-34 source assignments 10-5 source bits 10-3, c-2 source register 10-2, c-2 interrupt request enable bit 12-6, c-32 interval count field 12-8, c-33 interval mode 12-3, 12-10 serial peripheral interface. see ispi interval mode enable bit 12-8, c-33 interval timer. see pit intsrc 10-2, c-2 ir 16-18, c-52 iren bit 11-11, c-39 irq bit 12-9, c-34 irq en bit 15-4, c-24 irq_en bit 12-6, c-32 irts bit 11-2, 11-12, c-41 ispi 12-1 block diagram 12-1 clock 12-4 control register 12-5, c-31 data register 12-5, c-30 debug mode and 12-11 enable bit 12-6, c-31 enable signal 12-4 general-purpose output 12-4 interval control register 12-8, c-33 interval mode 12-3, 12-10 low-power modes and 8-5 low-power operation 12-11 manual mode 12-2, 12-9 operation 12-1 programming model 12-4, c-30 signals 12-3 slave mode 12-3, 12-10 status register 12-8, c-34 timing specifications a-6 itadr 9-12, 9-16, c-13 itcsr 9-14, c-11 itdr 9-12, 9-15, c-12 itie bit 9-13, 9-14, c-12 itif bit 9-13, 9-14, c-12 ivl_en bit 12-8, c-33 CjC jtag test access port 16-1 CkC kcdd bits 14-5, c-15 kco bits 14-3, c-14 kddr 14-5, c-15 kdie bit 14-4, c-14 kdsc bit 14-4, c-15 key depress interrupt enable bit 14-4, c-14 key depress synchronizer clear bit 14-4, c-15 key release interrupt enable bit 14-4, c-14 keypad column data direction bits 14-5, c-15 column strobe open-drain enable bits 14-3, c-14 control register 14-2, c-14 data direction register 14-5, c-15 data register 14-5, c-15 key depress bit 14-3, 14-4, c-15 key release bit 14-3, 14-4, c-15 row data direction bits 14-5, c-15 row enable bits 14-3, c-14 status register 14-3, c-14 keypad port. see kpp kpcr 14-2, c-14 kpdr 14-5, c-15 kpkd bit 14-3, 14-4, c-15 kpkr bit 14-3, 14-4, c-15
motorola MMC2001 i-4 reference manual kpp 14-1 block diagram 14-1 configuration 14-6 low-power modes and 8-6 matrix construction 14-6 matrix scanning 14-6 multiple key closures 14-8 operation 14-6 programming model 14-2, c-13 signals 14-2 standby 14-7 kpsr 14-3, c-14 krdd bits 14-5, c-15 kre bits 14-3, c-14 krie bit 14-4, c-14 ClC level-sensitive interrupts 13-2, c-27 link register 2-3 load and store 2-2 load bit 15-4, c-24 load pwmpr and pwmwr bit 15-4, c-24 loop bit 11-15, c-44 loop ir bit 11-15, c-44 loop tx and rx for ir test bit 11-15, c-44 loop tx and rx for test bit 11-15, c-44 loopback bit 12-8, c-33 low_refclk 8-1 low-power modes 8-1, 8-4 ispi operation in 12-11 peripheral behavior 8-5 pwm operation in 15-8 uart operation in 11-23 low-voltage reset 4-5, 8-6 lpbk bit 12-8, c-33 lpmd (cpu) signals 8-4 lvrstin bit 9-4, c-6 lvrstin signal 4-5, 8-6 CmC m?core 2-1 architecture 2-2 bus interface 2-8 data format 2-5 instruction set 2-6 operand addressing 2-6 programming model 2-3 mal 16-13, c-51 manual mode 12-2, 12-9 master in, slave out 12-3 master mode bit 12-6, c-32 master out, slave in 12-4 maximum ratings a-1 mbca 16-14, c-51 mbcb 16-14, c-51 mbo bit 16-11, c-50 memory address latch 16-13, c-51 breakpoint 16-12 b, a control bits 16-10, c-49 b, a range control bits 16-10, c-49 counters 16-14, c-51 occurrence bit 16-11, c-50 load and store 2-2 map MMC2001 3-1 peripheral modules 3-2, c-1 organization 2-5 mfcr instruction 2-4 MMC2001 memory map 3-1 signals 4-1 mod timing specifications a-2 mod signal 4-4, 7-2, 7-6 mode bit 15-5, c-24 modules address map 3-2, c-1 interface operation 3-2 move from control register 2-4 move to control register 2-4 mstr bit 12-6, c-32 mtcr instruction 2-4 multiply 2-2 CnC nier 10-3, c-2 nipnd 10-4, c-4 normal interrupt enable register 10-3, c-2 pending flags 10-4, c-4 pending register 10-4, c-4 np flags 10-4, c-4 CoC ocmr 16-6, c-46 ocr 16-8, c-47 odec 16-12 oe assert bit 7-10, c-19 oe signal 4-4, 7-2 oea bit 7-10, c-19 once 16-1 block diagram 16-1 command register 16-6, c-46 commands 16-21 control register 16-8, c-47 controller 16-2, 16-5 debug output 16-6 decoder 16-12 interface signals 16-5 operation 16-1 serial interface 16-5 signals 16-3
MMC2001 motorola reference manual i-5 status register 16-11, c-50 timing specifications a-9 trace logic 16-14 on-chip emulation module. see once osr 16-11, c-50 otc 16-15 output enable 4-4, 7-2 overrun error 11-5 overrun flag 12-9, c-34 ovr bit 12-9, c-34 ovrrun bit 11-7, c-36 ovw bit 9-14, c-12 CpC pa bit 7-11, c-20 parity enable bit 11-12, c-41 error 11-5 error bit 11-8, c-37 odd/even bit 11-13, c-41 pc 2-2, 2-3, 16-18, c-51 pc fifo 16-20 pd bits 11-17, c-45 period field 15-6, c-26 peripheral modules address map 3-2, c-1 interface operation 3-2 pha bit 12-7, c-32 phase bit 12-7, c-32 pin assert bit 7-11, c-20 pipeline information 16-17 pipeline, execution 2-2 pit 9-11 alternate data register 9-12, 9-16, c-13 as a "free-running" timer 9-13 as a "set-and-forget" timer 9-12 block diagram 9-12 control/status register 9-14, c-11 data register 9-12, 9-15, c-12 enable bit 9-15, c-12 in debug mode 9-16 interrupt enable bit 9-13, 9-14, c-12 interrupt flag 9-13, 9-14, c-12 low-power modes and 9-16 operation 9-12 registers 9-13 pm field 16-12, c-51 pol bit 12-7, 15-5, c-24, c-32 polarity bit 12-7, 15-5, c-24, c-32 por bit 9-4, c-6 port data bits 11-17, c-45 positive supply 4-9 power and ground pins 4-9 power-on reset bit 9-4, c-6 prefetch size field 16-19, c-52 prefetch transfer code field 16-19, c-53 pren bit 11-12, c-41 prerr bit 11-8, c-37 prescaler, pwm 15-2 privilege modes 2-3 supervisor 2-3 user 2-3 processor mode field 16-12, c-51 processor status register 16-19, c-53 proe bit 11-13, c-41 program counter 2-2, 2-3 program counter register 16-18, c-51 programming model edge port 13-2 eim 7-7 interrupt controller 10-2 ispi 12-4, c-30 kpp 14-2, c-13 m?core 2-3 pwm 15-2, c-22 timer/reset module 9-1, c-5 uart 11-5 watchdog timer 9-10 psr 16-19, c-53 pstat signals 16-5 pulse period field 15-6, c-26 pulse width field 15-7, c-26 pulse width modulator. see pwm pwm 15-1 block diagram 15-1 control register 15-4, c-23 counter register 15-7, c-27 data bit 15-5, c-24 generating audio 15-1 interrupt request bit 15-4, c-24 irq bit 15-4, c-24 low-power modes and 8-5, 15-8 mode bit 15-5, c-24 operating range 15-8 period register 15-6, c-25 prescaler 15-2 programming model 15-2, c-22 width register 15-7, c-26 pwm signals 4-8 pwmcr 15-4, 15-7, c-23, c-27 pwmpr 15-6, c-25 pwmwr 15-7, c-26 CrC r/w bit 16-7, c-46 r/w signal 4-4, 7-2 r0 (stack pointer) 2-3, 2-6 r15 (link register) 2-3 rca bit 16-10, c-49 rcb bit 16-10, c-49 read/write 7-2 enable 4-4 read/write command bit 16-7, c-46 receive data 4-7, 11-3 receive data register 12-5, c-30 received data bits 11-8, c-37 receiver 11-3 enable bit 11-10, c-39
motorola MMC2001 i-6 reference manual fifo interrupt trigger level bits 11-10, c-39 overrun bit 11-7, c-36 ready interrupt enable bit 11-10, c-39 ready interrupt flag 11-14, c-43 register select field 16-7, c-46 request to send 4-8, 11-2 reset 4-4 block diagram 9-2 out 4-5 pins 9-2 sequence 9-3 source/chip configuration register 9-3, c-6 sources 9-2 timing specifications a-2 return from exception 2-3 from fast interrupt 2-3 rfi instruction 2-3 risc 2-1 rld bit 9-12, 9-13, 9-15, c-12 rom module 5-1 row senses 4-7 rrdy bit 11-14, c-43 rrdyen bit 11-10, c-39 rs field 16-7, c-46 rscr 9-3, c-6 rst bit 9-4, c-6 rstin signal 4-4, 9-4, c-6 rstout signal 4-5 rte instruction 2-3 rts delta bit 11-15, c-43 rts delta interrupt enable bit 11-11, c-39 rts pin status bit 11-14, c-43 rts signal 11-2 rts0 4-8 rtsd bit 11-15, c-43 rtsd en bit 11-11, c-39 rtss bit 11-14, c-43 run mode 8-4 rx data bits 11-8, c-37 rx data register 12-5, c-30 rxd signals 4-7, 11-3 rxen bit 11-10, c-39 rxfl bit 11-10, c-39 CsC s bit 2-3 scratch registers 2-3, 2-4 send break bit 11-11, c-40 sequential breakpoint a, b arm occurrence bits 16-12, c-51 sequential control field 16-9, c-48 serial protocol, once 16-21 shadow registers 2-3, 2-4 shen bits 7-7, 7-12, c-22 show cycle enable bits 7-7, 7-12, c-22 signals 4-1 edge port 13-1 eim 7-1 ispi 12-3 kpp 14-2 m?core bus 2-9 once 16-3 uart 11-2 slave mode 12-3, 12-10 sndbrk bit 11-11, c-40 sns bit 12-6, c-31 software debug occurrence bit 16-11, c-50 sp bit 7-6, 7-10, c-19 spcr 12-5, c-31 spdr 12-5, c-30 spi data master in/slave out 4-8 data master out/slave in 4-8 enable 4-8 general-purpose output 4-8 serial clock 4-8 spi_clk signal 4-8, 12-4 spi_en bit 12-6, c-31 spi_en sense bit 12-6, c-31 spi_en signal 4-8, 12-4 spi_gp control bit 12-7, c-32 spi_gp signal 4-8, 12-4 spi_miso signal 4-8, 12-3 spi_mosi signal 4-8, 12-4 spicr 12-8, c-33 spigp bit 12-7, c-32 spram bit 7-12, c-21 sprom bit 7-12, c-21 spsr 12-8, c-34 sqa bit 16-12, c-51 sqb bit 16-11, c-50 sqc field 16-9, c-48 sram 6-1 stack pointer 2-3, 2-6 standby battery power 4-9 standby mode 8-6 standby power filter 4-9 start bit 11-4 static ram 6-1 status registers 2-3 stop bit 11-4 stop bit (pit) 9-14, c-11 stop bits 11-13, c-41 stop mode 8-4 stpb bit 11-13, c-41 subroutine calls 2-3 supervisor mode 2-3 supervisor protect bit 7-6, 7-10, c-19 swo bit 16-11, c-50 sz field 16-19, c-52 CtC tap 16-1 tc field 16-19, c-53 tck 4-5 tck signal 16-3 tdi signal 4-5, 16-3
MMC2001 motorola reference manual i-7 tdo signal 4-6, 16-3 tea signal 7-6 test 4-6 test clock 4-5 data input 4-5 data output 4-6 mode select 4-6 reset 4-6, 16-4 time-of-day timer. see tod timer/reset module 9-1 programming model 9-1, c-5 tme bit 16-9, c-48 tms signal 4-6, 16-3 to bit 16-11, c-50 tod 9-4 control/status register 9-5, c-7 fraction alarm register 9-5, 9-7, c-9 fraction register 9-5, 9-6, c-8 low-power modes and 8-6, 9-5 seconds alarm register 9-5, 9-7, c-8 seconds register 9-5, 9-6, c-8 todfar 9-5, 9-7, c-9 todfr 9-5, 9-6, c-8 todsar 9-5, 9-7, c-8 todscr 9-5, c-7 todsr 9-5, 9-6, c-8 trace count occurrence bit 16-11, c-50 counter 16-15 logic, once 16-14 mode enable bit 16-9, c-48 transfer error acknowledge 7-6 transmit data 4-7, 11-3 transmit data bits 11-9, c-38 transmit data register 12-5, c-30 transmitter 11-3 empty bit 11-14, c-43 enable bit 11-10, c-38 fifo interrupt trigger level bits 11-9, c-38 ready interrupt enable bit 11-10, c-38 ready interrupt flag 11-14, c-43 trdy bit 11-14, c-43 trdyen bit 11-10, c-38 trst signal 4-6, 16-4 tx data bits 11-9, c-38 tx data register 12-5, c-30 txd signals 4-7, 11-3 txen bit 11-10, c-38 txfl bit 11-9, c-38 txmpty bit 11-14, c-43 CuC uart 11-1 block diagram 11-2 brg register 11-13, c-42 control register 1 11-9, c-38 control register 2 11-11, c-40 data direction register 11-16 debug mode and 11-24 enable bit 11-11, c-40 general-purpose i/o 11-16 low-power modes and 8-5, 11-23 port control register 11-16, c-44 port data register 11-17, c-45 programming model 11-5 receiver register 11-7, c-36 signals 11-2 status register 11-14, c-42 test register 11-15, c-43 transmitter register 11-8, c-37 ubrgr 11-13, c-42 ucr1 11-9, c-38 ucr2 11-11, c-40 uddr 11-16 upcr 11-16, c-44 updr 11-17, c-45 urx 11-7, c-36 user mode 2-3 usr 11-14, c-42 uts 11-15, c-43 utx 11-8, c-37 CvC v batt 4-9 v dd 4-9 v stby 4-9 CwC wait mode 8-4 wait-state control bit 7-8, c-17 watchdog 7-6, 9-8 control register 9-10, c-9 debug enable bit 9-11, c-10 debug mode and 9-10 doze enable bit 9-11, c-10 doze mode and 9-9 enable bit 9-11, c-10 low-power modes and 8-6 programming model 9-10 reset bit 9-4, 9-11, c-6, c-10 reset, following 9-9 service operation 9-9 service register 9-11, c-10 stop enable bit 9-11, c-10 stop mode and 9-9 time-out field 9-10, c-10 wait mode and 9-9 wbbr 16-19, c-53 wcr 9-10, c-9 wdbg bit 9-11, c-10 wde bit 9-11, c-10 wdr bit 9-4, 9-11, c-6, c-10 wdze bit 9-11, c-10 wen bit 7-10, c-19 width field 15-7, c-26
motorola MMC2001 i-8 reference manual word size bit 11-13, c-42 wp bit 7-6, 7-11, c-20 write protect bit 7-6, 7-11, c-20 write wait state bit 7-9, c-18 write-back bus register 16-17, 16-19, c-53 ws bit 11-13, c-42 wsc bit 7-8, c-17 wsr 9-11, c-10 wstp bit 9-11, c-10 wt field 9-10, c-10 wws bit 7-9, c-18 CxC xch bit 12-9, c-34 xoscpin 4-5
MMC2001 record of changes motorola reference manual r-1 record of changes the MMC2001 reference manual (MMC2001rm/d) is a new document.
motorola record of changes MMC2001 r-2 reference manual this manual is a product of the motorola m?core technology center design documentation team. technical writing, illustration, and production editing performed with adobe? framemaker? running on multiple platforms. cover graphic design by bazzirk, inc. of austin, texas. printed by imperial lithographics, phoenix, arizona.

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